Nicolas Pitre 7f74825958 riscv: add a qemu_riscv64 board ... This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board. Memory is tight so a few tests had to be disabled due to the extra memory usage compared to qemu_riscv32. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>		2019-08-09 09:11:45 -05:00
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hifive1	riscv: freedom: rename RISCV32 to RISCV	2019-08-08 00:29:24 -04:00
hifive1_revb	riscv: freedom: rename RISCV32 to RISCV	2019-08-08 00:29:24 -04:00
litex_vexriscv	riscv32: rename to riscv	2019-08-02 13:54:48 -07:00
m2gl025_miv	riscv32: rename to riscv	2019-08-02 13:54:48 -07:00
qemu_riscv32	riscv: freedom: rename RISCV32 to RISCV	2019-08-08 00:29:24 -04:00
qemu_riscv64	riscv: add a qemu_riscv64 board	2019-08-09 09:11:45 -05:00
rv32m1_vega	soc: riscv32: fix zero-riscy zephyr,flash node	2019-08-07 07:27:51 -05:00
index.rst	riscv32: rename to riscv	2019-08-02 13:54:48 -07:00