263 lines
7.4 KiB
C
263 lines
7.4 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2021 Linaro Limited
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* Copyright (c) 2021 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <drivers/pinctrl.h>
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#include <gpio/gpio_stm32.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_gpio.h>
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#include <stm32_ll_system.h>
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/**
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* @brief Array containing pointers to each GPIO port.
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*
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* Entries will be NULL if the GPIO port is not enabled.
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*/
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static const struct device * const gpio_ports[] = {
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioa)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiob)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioc)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiod)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioe)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiof)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiog)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioh)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioi)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioj)),
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DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiok)),
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};
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/** Number of GPIO ports. */
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static const size_t gpio_ports_cnt = ARRAY_SIZE(gpio_ports);
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11)
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#define REMAP_PA11 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11)
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa12)
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#define REMAP_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa12)
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#endif
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
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#define REMAP_PA11_PA12 DT_PROP(DT_NODELABEL(pinctrl), remap_pa11_pa12)
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#endif
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#if REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12
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int stm32_pinmux_init_remap(const struct device *dev)
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{
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ARG_UNUSED(dev);
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#if REMAP_PA11 || REMAP_PA12
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#if !defined(CONFIG_SOC_SERIES_STM32G0X)
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#error "Pin remap property available only on STM32G0 SoC series"
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#endif
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
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#if REMAP_PA11
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LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA11);
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#endif
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#if REMAP_PA12
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LL_SYSCFG_EnablePinRemap(LL_SYSCFG_PIN_RMP_PA12);
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#endif
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#elif REMAP_PA11_PA12
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#if !defined(SYSCFG_CFGR1_PA11_PA12_RMP)
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#error "Pin remap property available only on STM32F070x SoC series"
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#endif
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
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LL_SYSCFG_EnablePinRemap();
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#endif /* (REMAP_PA11 || REMAP_PA12) || REMAP_PA11_PA12 */
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return 0;
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}
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SYS_INIT(stm32_pinmux_init_remap, PRE_KERNEL_1,
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CONFIG_PINCTRL_STM32_REMAP_INIT_PRIORITY);
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#endif /* REMAP_PA11 || REMAP_PA12 || REMAP_PA11_PA12 */
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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/* ignore swj-cfg reset state (default value) */
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#if ((DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), swj_cfg)) && \
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(DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) != 0))
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static int stm32f1_swj_cfg_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
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/* reset state is '000' (Full SWJ, (JTAG-DP + SW-DP)) */
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/* only one of the 3 bits can be set */
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#if (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 1)
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/* 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST */
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/* releases: PB4 */
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LL_GPIO_AF_Remap_SWJ_NONJTRST();
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#elif (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 2)
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/* 010: JTAG-DP Disabled and SW-DP Enabled */
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/* releases: PB4 PB3 PA15 */
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LL_GPIO_AF_Remap_SWJ_NOJTAG();
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#elif (DT_ENUM_IDX(DT_NODELABEL(pinctrl), swj_cfg) == 3)
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/* 100: JTAG-DP Disabled and SW-DP Disabled */
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/* releases: PB4 PB3 PA13 PA14 PA15 */
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LL_GPIO_AF_DisableRemap_SWJ();
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#endif
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return 0;
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}
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SYS_INIT(stm32f1_swj_cfg_init, PRE_KERNEL_1, 0);
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#endif /* DT_NODE_HAS_PROP(DT_NODELABEL(pinctrl), swj_cfg) */
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/**
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* @brief Helper function to check and apply provided pinctrl remap
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* configuration.
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*
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* Check operation verifies that pin remapping configuration is the same on all
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* pins. If configuration is valid AFIO clock is enabled and remap is applied
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*
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* @param pins List of pins to be configured.
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* @param pin_cnt Number of pins.
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*
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* @retval 0 If successful
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* @retval -EINVAL If pins have an incompatible set of remaps.
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*/
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static int stm32_pins_remap(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt)
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{
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uint32_t reg_val;
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uint16_t remap;
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remap = (uint16_t)STM32_DT_PINMUX_REMAP(pins[0].pinmux);
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/* not remappable */
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if (remap == NO_REMAP) {
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return 0;
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}
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for (size_t i = 1U; i < pin_cnt; i++) {
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if (STM32_DT_PINMUX_REMAP(pins[i].pinmux) != remap) {
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return -EINVAL;
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}
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}
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/* A valid remapping configuration is available */
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/* Apply remapping before proceeding with pin configuration */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
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if (STM32_REMAP_REG_GET(remap) == 0U) {
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/* read initial value, ignore write-only SWJ_CFG */
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reg_val = AFIO->MAPR & ~AFIO_MAPR_SWJ_CFG;
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reg_val |= STM32_REMAP_VAL_GET(remap) << STM32_REMAP_SHIFT_GET(remap);
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/* apply undocumented '111' (AFIO_MAPR_SWJ_CFG) to affirm SWJ_CFG */
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/* the pins are not remapped without that (when SWJ_CFG is not default) */
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AFIO->MAPR = reg_val | AFIO_MAPR_SWJ_CFG;
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} else {
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reg_val = AFIO->MAPR2;
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reg_val |= STM32_REMAP_VAL_GET(remap) << STM32_REMAP_SHIFT_GET(remap);
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AFIO->MAPR2 = reg_val;
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}
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return 0;
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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static int stm32_pin_configure(uint32_t pin, uint32_t pin_cgf, uint32_t pin_func)
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{
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const struct device *port_device;
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if (STM32_PORT(pin) >= gpio_ports_cnt) {
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return -EINVAL;
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}
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port_device = gpio_ports[STM32_PORT(pin)];
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if ((port_device == NULL) || (!device_is_ready(port_device))) {
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return -ENODEV;
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}
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return gpio_stm32_configure(port_device, STM32_PIN(pin), pin_cgf, pin_func);
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
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uint32_t pin, mux;
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uint32_t pin_cgf = 0;
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int ret = 0;
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ARG_UNUSED(reg);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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ret = stm32_pins_remap(pins, pin_cnt);
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if (ret < 0) {
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return ret;
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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mux = pins[i].pinmux;
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
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uint32_t pupd;
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if (STM32_DT_PINMUX_FUNC(mux) == ALTERNATE) {
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pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_ALT_FUNC;
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} else if (STM32_DT_PINMUX_FUNC(mux) == ANALOG) {
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pin_cgf = pins[i].pincfg | STM32_MODE_INPUT | STM32_CNF_IN_ANALOG;
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} else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_IN) {
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pin_cgf = pins[i].pincfg | STM32_MODE_INPUT;
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pupd = pin_cgf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
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if (pupd == STM32_PUPD_NO_PULL) {
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pin_cgf = pin_cgf | STM32_CNF_IN_FLOAT;
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} else {
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pin_cgf = pin_cgf | STM32_CNF_IN_PUPD;
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}
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} else if (STM32_DT_PINMUX_FUNC(mux) == GPIO_OUT) {
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pin_cgf = pins[i].pincfg | STM32_MODE_OUTPUT | STM32_CNF_GP_OUTPUT;
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} else {
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/* Not supported */
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__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
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}
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#else
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if (STM32_DT_PINMUX_FUNC(mux) < STM32_ANALOG) {
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pin_cgf = pins[i].pincfg | STM32_MODER_ALT_MODE;
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} else if (STM32_DT_PINMUX_FUNC(mux) == STM32_ANALOG) {
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pin_cgf = STM32_MODER_ANALOG_MODE;
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} else if (STM32_DT_PINMUX_FUNC(mux) == STM32_GPIO) {
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uint32_t gpio_out = pins[i].pincfg &
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(STM32_ODR_MASK << STM32_ODR_SHIFT);
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if (gpio_out != 0) {
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pin_cgf = pins[i].pincfg | STM32_MODER_OUTPUT_MODE;
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} else {
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pin_cgf = pins[i].pincfg | STM32_MODER_INPUT_MODE;
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}
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} else {
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/* Not supported */
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__ASSERT_NO_MSG(STM32_DT_PINMUX_FUNC(mux));
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}
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
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pin = STM32PIN(STM32_DT_PINMUX_PORT(mux),
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STM32_DT_PINMUX_LINE(mux));
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ret = stm32_pin_configure(pin, pin_cgf, STM32_DT_PINMUX_FUNC(mux));
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if (ret < 0) {
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return ret;
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}
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}
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return 0;
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}
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