150 lines
4.5 KiB
C
150 lines
4.5 KiB
C
/*
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* Copyright (c) 2016 Wind River Systems, Inc.
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* Copyright (c) 2020 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* this file is only meant to be included by kernel_structs.h */
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#ifndef ZEPHYR_ARCH_XTENSA_INCLUDE_KERNEL_ARCH_FUNC_H_
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#define ZEPHYR_ARCH_XTENSA_INCLUDE_KERNEL_ARCH_FUNC_H_
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#ifndef _ASMLANGUAGE
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#include <kernel_internal.h>
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#include <string.h>
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#include <zephyr/cache.h>
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#include <zephyr/zsr.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS,
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CONFIG_ISR_STACK_SIZE);
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static ALWAYS_INLINE void arch_kernel_init(void)
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{
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}
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void xtensa_switch(void *switch_to, void **switched_from);
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static ALWAYS_INLINE void arch_switch(void *switch_to, void **switched_from)
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{
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xtensa_switch(switch_to, switched_from);
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}
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#ifdef CONFIG_KERNEL_COHERENCE
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static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread,
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void *old_switch_handle,
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struct k_thread *new_thread)
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{
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int32_t curr_cpu = _current_cpu->id;
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size_t ostack = old_thread->stack_info.start;
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size_t osz = old_thread->stack_info.size;
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size_t osp = (size_t) old_switch_handle;
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size_t nstack = new_thread->stack_info.start;
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size_t nsz = new_thread->stack_info.size;
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size_t nsp = (size_t) new_thread->switch_handle;
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int zero = 0;
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__asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(zero));
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if (old_switch_handle != NULL) {
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int32_t a0save;
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__asm__ volatile("mov %0, a0;"
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"call0 xtensa_spill_reg_windows;"
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"mov a0, %0"
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: "=r"(a0save));
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}
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/* The following option ensures that a living thread will never
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* be executed in a different CPU so we can safely return without
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* invalidate and/or flush threads cache.
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*/
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if (IS_ENABLED(CONFIG_SCHED_CPU_MASK_PIN_ONLY)) {
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return;
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}
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/* The "live" area (the region between the switch handle,
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* which is the stack pointer, and the top of the stack
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* memory) of the inbound stack needs to be invalidated if we
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* last ran on another cpu: it may contain data that was
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* modified there, and our cache may be stale.
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*
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* The corresponding "dead area" of the inbound stack can be
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* ignored. We may have cached data in that region, but by
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* definition any unused stack memory will always be written
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* before being read (well, unless the code has an
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* uninitialized data error) so our stale cache will be
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* automatically overwritten as needed.
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*/
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if (curr_cpu != new_thread->arch.last_cpu) {
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sys_cache_data_invd_range((void *)nsp, (nstack + nsz) - nsp);
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}
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old_thread->arch.last_cpu = curr_cpu;
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/* Dummy threads appear at system initialization, but don't
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* have stack_info data and will never be saved. Ignore.
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*/
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if (old_thread->base.thread_state & _THREAD_DUMMY) {
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return;
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}
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/* For the outbound thread, we obviousy want to flush any data
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* in the live area (for the benefit of whichever CPU runs
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* this thread next). But we ALSO have to invalidate the dead
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* region of the stack. Those lines may have DIRTY data in
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* our own cache, and we cannot be allowed to write them back
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* later on top of the stack's legitimate owner!
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*
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* This work comes in two flavors. In interrupts, the
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* outgoing context has already been saved for us, so we can
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* do the flush right here. In direct context switches, we
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* are still using the stack, so we do the invalidate of the
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* bottom here, (and flush the line containing SP to handle
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* the overlap). The remaining flush of the live region
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* happens in the assembly code once the context is pushed, up
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* to the stack top stashed in a special register.
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*/
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if (old_switch_handle != NULL) {
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sys_cache_data_flush_range((void *)osp, (ostack + osz) - osp);
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sys_cache_data_invd_range((void *)ostack, osp - ostack);
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} else {
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/* When in a switch, our current stack is the outbound
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* stack. Flush the single line containing the stack
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* bottom (which is live data) before invalidating
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* everything below that. Remember that the 16 bytes
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* below our SP are the calling function's spill area
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* and may be live too.
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*/
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__asm__ volatile("mov %0, a1" : "=r"(osp));
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osp -= 16;
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sys_cache_data_flush_range((void *)osp, 1);
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sys_cache_data_invd_range((void *)ostack, osp - ostack);
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uint32_t end = ostack + osz;
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__asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(end));
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}
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}
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#endif
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static inline bool arch_is_in_isr(void)
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{
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return arch_curr_cpu()->nested != 0U;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_KERNEL_ARCH_FUNC_H_ */
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