60 lines
1.3 KiB
C
60 lines
1.3 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __CC1200_H__
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#define __CC1200_H__
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#include <device.h>
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/* RF settings
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*
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* First 42 entries are for the 42 first registers from
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* address 0x04 to 0x2D included.
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* Next, the last 58 entries are for the 58 registers from
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* extended address 0x00 to 0x39 included
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*
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* If CONFIG_IEEE802154_CC1200_RF_PRESET is not used, one will need
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* no provide 'cc1200_rf_settings' with proper settings. These can
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* be generated through TI's SmartRF application.
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*
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*/
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struct cc1200_rf_registers_set {
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u32_t chan_center_freq0;
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u16_t channel_limit;
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/* to fit in u16_t, spacing is a multiple of 100 Hz,
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* 12.5KHz for instance will be 125.
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*/
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u16_t channel_spacing;
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u8_t registers[100];
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};
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#ifndef CONFIG_IEEE802154_CC1200_RF_PRESET
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extern const struct cc1200_rf_registers_set cc1200_rf_settings;
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#endif
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/* Note for EMK & EM adapter booster pack users:
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* SPI pins are easy, RESET as well, but when it comes to GPIO:
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* CHIP -> EM adapter
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* GPIO0 -> GPIOA
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* GPIO1 -> reserved (it's SPI MISO)
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* GPIO2 -> GPIOB
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* GPIO3 -> GPIO3
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*/
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enum cc1200_gpio_index {
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CC1200_GPIO_IDX_GPIO0,
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CC1200_GPIO_IDX_MAX,
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};
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struct cc1200_gpio_configuration {
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struct device *dev;
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u32_t pin;
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};
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struct cc1200_gpio_configuration *cc1200_configure_gpios(void);
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#endif /* __CC1200_H__ */
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