zephyr/arch/riscv/core
Jamie McCrae 9c68231ba9 soc: openisa_rv32m1: Port to HWMv2
Ports the SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-03-01 15:49:58 +01:00
..
offsets arch: riscv: offsets: fix header race condition 2024-01-19 15:13:53 +00:00
CMakeLists.txt
asm_macros.inc
coredump.c
cpu_idle.c arch: riscv: idle: trace idle and call wfi 2024-01-12 09:58:31 +01:00
fatal.c soc: openisa_rv32m1: Port to HWMv2 2024-03-01 15:49:58 +01:00
fpu.S
fpu.c arch: smp: make flush_fpu_ipi a common, optional interfaces 2024-01-09 10:00:17 +01:00
irq_manage.c riscv: irq: Set prio for dynamic and direct irqs on clic 2024-01-18 10:53:27 +01:00
irq_offload.c
isr.S arch: riscv: make __soc_is_irq optional 2024-01-23 09:57:57 +01:00
pmp.S
pmp.c riscv: pmp: Fix assertion for PMP misaligned start address and size 2023-10-25 10:05:24 +02:00
prep_c.c arch: riscv: define local soc_interrupt_init prototypes 2024-01-15 09:58:03 +01:00
reboot.c
reset.S arch: introduce arch_secondary_cpu_init 2024-01-09 10:00:17 +01:00
semihost.c
smp.c arch: riscv: smp: define MSIP_BASE 2024-01-19 15:13:53 +00:00
switch.S
thread.c
tls.c
userspace.S
vector_table.ld