zephyr/arch/riscv
Jamie McCrae 9c68231ba9 soc: openisa_rv32m1: Port to HWMv2
Ports the SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-03-01 15:49:58 +01:00
..
core soc: openisa_rv32m1: Port to HWMv2 2024-03-01 15:49:58 +01:00
include arch: smp: make flush_fpu_ipi a common, optional interfaces 2024-01-09 10:00:17 +01:00
CMakeLists.txt riscv: syscalls: use zephyr_syscall_header 2023-06-17 07:57:45 -04:00
Kconfig arch: riscv: always use 'riscv' for CONFIG_ARCH 2024-02-26 12:49:06 +01:00
Kconfig.core riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
Kconfig.isa riscv: Introduce BitManip extensions 2022-08-29 16:57:18 +02:00