zephyr/arch/xtensa/soc/intel_s1000
Sathish Kuttan 824bcaca52 xtensa: intel_s1000: Add SoC level SYS_INIT
Added a SYS_INIT for SoC level initialization of Intel S1000
Added routines for setting up resource ownership for
    DMA, I2S
Added routine to setup power gating and clock configuration

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-08-19 11:06:09 -07:00
..
CMakeLists.txt cmake: replace PROJECT_SOURCE_DIR with ZEPHYR_BASE 2018-06-18 15:25:55 -04:00
Kconfig.defconfig soc: defconfig: Consistently quote string defaults 2018-05-26 19:17:48 -04:00
Kconfig.soc
dts.fixup DTS: intel_s1000: Clean up I2C and UART stuff from soc.h 2018-06-11 17:27:58 -04:00
linker.ld cmake: LD: Specify the entry point in the linker scripts 2018-07-03 17:18:14 -04:00
memory.h dts: xtensa: Add device tree support for xtensa 2018-05-01 16:46:41 -04:00
soc.c xtensa: intel_s1000: Add SoC level SYS_INIT 2018-08-19 11:06:09 -07:00
soc.h xtensa: intel_s1000: Add SoC level SYS_INIT 2018-08-19 11:06:09 -07:00