zephyr/arch/riscv/core
Kumar Gala 3369997dd2 arch: riscv: Convert to CONFIG_MP_MAX_NUM_CPUS
Convert CONFIG_MP_NUM_CPUS to CONFIG_MP_MAX_NUM_CPUS as we work on
phasing out CONFIG_MP_NUM_CPUS.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-10-25 10:52:25 +02:00
..
offsets riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
CMakeLists.txt arch: riscv: core: Place vectors section through zephyr_linker_sources() 2022-09-08 10:39:31 +02:00
asm_macros.inc riscv: abstract RV32E register access 2022-06-23 13:12:05 -04:00
coredump.c riscv: Introduce support for RV32E 2022-06-08 18:50:22 +09:00
cpu_idle.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
fatal.c include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
irq_manage.c include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
irq_offload.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
isr.S soc: riscv: remove usage of SOC_ERET 2022-08-04 13:44:48 +02:00
pmp.S include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
pmp.c riscv: pmp: fix stackguard when used on SMP 2022-09-28 07:53:56 +00:00
prep_c.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reboot.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reset.S arch: riscv: Convert to CONFIG_MP_MAX_NUM_CPUS 2022-10-25 10:52:25 +02:00
semihost.c arch: riscv: Align semihost_exec function at 16-byte boundary 2022-08-08 10:52:34 +02:00
smp.c smp: Move for loops to use arch_num_cpus instead of CONFIG_MP_NUM_CPUS 2022-10-21 13:14:58 +02:00
switch.S riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
thread.c include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
tls.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
userspace.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
vector_table.ld arch: riscv: core: Place vectors section through zephyr_linker_sources() 2022-09-08 10:39:31 +02:00