98 lines
2.6 KiB
Plaintext
98 lines
2.6 KiB
Plaintext
# XTENSA architecture configuration options
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "XTENSA Options"
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depends on XTENSA
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config ARCH
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default "xtensa"
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config SIMULATOR_XTENSA
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bool "Simulator Configuration"
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help
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Specify if the board configuration should be treated as a simulator.
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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prompt "Hardware clock cycles per second, 2000000 for ISS"
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default 2000000
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range 1000000 1000000000
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help
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This option specifies hardware clock.
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config XTENSA_NO_IPC
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bool "Core has no IPC support"
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select ATOMIC_OPERATIONS_C
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help
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Uncheck this if your core does not implement "SCOMPARE1" register and "s32c1i"
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instruction.
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config XTENSA_RESET_VECTOR
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bool "Build reset vector code"
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default y
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help
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This option controls whether the initial reset vector code is built.
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This is always needed for the simulator. Real boards may already
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implement this in boot ROM.
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config XTENSA_USE_CORE_CRT1
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bool "Use crt1.S from core"
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default y
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help
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SoC or boards might define their own __start by setting this setting
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to false.
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config XTENSA_ENABLE_BACKTRACE
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bool "Backtrace on panic exception"
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default y
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depends on SOC_ESP32 || SOC_FAMILY_INTEL_ADSP
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help
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Enable this config option to print backtrace on panic exception
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config XTENSA_CPU_IDLE_SPIN
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bool "Use busy loop for k_cpu_idle"
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help
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Use a spin loop instead of WAITI for the CPU idle state.
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config XTENSA_WAITI_BUG
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bool "Workaround sequence for WAITI bug on LX6"
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help
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SOF traditionally contains this workaround on its ADSP
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platforms which prefixes a WAITI entry with 128 NOP
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instructions followed by an ISYNC and EXTW.
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config XTENSA_SMALL_VECTOR_TABLE_ENTRY
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bool "Workaround for small vector table entries"
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help
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This option enables a small indirection to bypass the size
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constraint of the vector table entry and moved the default
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handlers to the end of vector table, renaming them to
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_Level\LVL\()VectorHelper.
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config XTENSA_CACHED_REGION
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int "Cached RPO mapping"
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range 0 7
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help
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A design trick on multi-core hardware is to map memory twice
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so that it can be seen in both (incoherent) cached mappings
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and a coherent "shared" area. This specifies which 512M
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region (0-7, as defined by the Xtensa Region Protection
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Option) contains the "cached" mapping.
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config XTENSA_UNCACHED_REGION
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int "Uncached RPO mapping"
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range 0 7
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help
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As for XTENSA_CACHED_REGION, this specifies which 512M
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region (0-7) contains the "uncached" mapping.
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config XTENSA_CCOUNT_HZ
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int "CCOUNT cycle rate"
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default 1000000
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help
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Rate in HZ of the Xtensa core as measured by the value of
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the CCOUNT register.
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endmenu
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