56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright(c) 2018 Intel Corporation. All rights reserved.
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*
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* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
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* Keyon Jie <yang.jie@linux.intel.com>
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* Rander Wang <rander.wang@intel.com>
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* Janusz Jankowski <janusz.jankowski@linux.intel.com>
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*/
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#include <device.h>
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#include <init.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(sof);
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#include <ipc.h>
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#include <soc/shim.h>
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#include <adsp/io.h>
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#include <cavs/mailbox.h>
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/*
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* Sets up the host windows so that the host can see the memory
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* content on the DSP SRAM.
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*/
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static void prepare_host_windows(void)
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{
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/* window0, for fw status */
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sys_write32((HP_SRAM_WIN0_SIZE | 0x7), DMWLO(0));
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sys_write32((HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE),
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DMWBA(0));
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memset((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END), 0,
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HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
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SOC_DCACHE_FLUSH((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
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HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
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/* window3, for trace
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* zeroed by trace initialization
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*/
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sys_write32((HP_SRAM_WIN3_SIZE | 0x7), DMWLO(3));
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sys_write32((HP_SRAM_WIN3_BASE | DMWBA_READONLY | DMWBA_ENABLE),
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DMWBA(3));
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memset((void *)HP_SRAM_WIN3_BASE, 0, HP_SRAM_WIN3_SIZE);
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SOC_DCACHE_FLUSH((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
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}
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static int adsp_init(const struct device *dev)
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{
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prepare_host_windows();
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return 0;
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}
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/* Init after IPM initialization and before logging (uses memory windows) */
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SYS_INIT(adsp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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