98 lines
2.0 KiB
Plaintext
98 lines
2.0 KiB
Plaintext
/*
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* Copyright (c) 2023 Meta
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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clock-frequency = <0>;
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compatible = "renode,virt", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv32imac_zicsr_zifencei";
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hlic: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "renode,virt-soc", "simple-bus";
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ranges;
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flash0: flash@80000000 {
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compatible = "soc-nv-flash";
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reg = <0x80000000 DT_SIZE_M(4)>;
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};
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sram0: memory@80400000 {
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compatible = "mmio-sram";
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reg = <0x80400000 DT_SIZE_M(4)>;
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};
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clint: clint@2000000 {
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compatible = "sifive,clint0";
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interrupts-extended = <&hlic 3>, <&hlic 7>;
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reg = <0x2000000 0x10000>;
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};
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plic0: interrupt-controller@c000000 {
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compatible = "sifive,plic-1.0.0";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts-extended = <&hlic 11>;
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reg = <0xc000000 0x04000000>;
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riscv,max-priority = <1>;
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riscv,ndev = <1023>;
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};
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plic1: interrupt-controller@8000000 {
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compatible = "sifive,plic-1.0.0";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts-extended = <&hlic 4>;
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reg = <0x8000000 0x04000000>;
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riscv,max-priority = <1>;
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riscv,ndev = <1023>;
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};
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uart0: uart@10000000 {
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interrupts = < 0x0a 1 >;
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interrupt-parent = < &plic0 >;
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clock-frequency = <150000000>;
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current-speed = <115200>;
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reg = < 0x10000000 0x100 >;
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compatible = "ns16550";
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reg-shift = < 0 >;
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status = "disabled";
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};
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uart1: uart@10000100 {
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interrupts = < 0x0a 1 >;
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interrupt-parent = < &plic1 >;
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clock-frequency = <150000000>;
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current-speed = <115200>;
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reg = < 0x10000100 0x100 >;
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compatible = "ns16550";
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reg-shift = < 0 >;
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status = "disabled";
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};
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};
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};
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