zephyr/dts/riscv
Fin Maaß de82190e13 drivers: clock_control: litex: remove redundant entry
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-07-12 05:49:01 -04:00
..
andes
efinix dts: riscv: Fix incorrect plic size 2024-07-02 22:21:17 -04:00
espressif soc: esp32c6: Kconfig and .ld updates, DTS and comments fix 2024-06-14 18:51:46 -04:00
gd
ite
lowrisc
microchip
niosv
nordic dts: nordic: Align boards dts to new VEVIF, BELLBOARD nomenclature 2024-06-15 04:41:47 -04:00
openisa soc/openisa: enable the `C` extension 2024-07-03 15:06:14 -04:00
qemu
sifive
starfive
telink
neorv32.dtsi
renode_riscv32_virt.dtsi
riscv32-litex-vexriscv.dtsi drivers: clock_control: litex: remove redundant entry 2024-07-12 05:49:01 -04:00