Wilfried Chauveau 29ffaaa0b6 arch: arm: cortex_m: Remove CPU_HAS_*CACHE from CPU_CORTEX_M7 ... Caches are optional on cortex-m7, having CPU_HAS_*CACHE in CPU_CORTEX_M7 definition renders them mandatory. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>		2023-12-05 10:19:15 +00:00
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arc	arch: introduce DSP_SHARING and CPU_HAS_DSP configs	2023-11-27 09:05:54 +00:00
arm	arch: arm: cortex_m: Remove CPU_HAS_*CACHE from CPU_CORTEX_M7	2023-12-05 10:19:15 +00:00
arm64	drivers: pinctrl: Add R-Car Gen4 support	2023-11-25 08:50:47 -05:00
mips	cmake: mips: update mips SoC to use SOC_LINKER_SCRIPT variable	2023-11-03 11:01:23 +01:00
nios2	cmake: cleanup and simplify the standard include logic in Zephyr	2023-11-06 18:57:30 -05:00
posix	arch posix: annotate posix_exit and nsi_exit as noreturn	2023-11-22 09:52:52 +01:00
riscv	soc: riscv: privileged: efinix-sapphire: Enable CONFIG_RISCV_HAS_CPU_IDLE	2023-11-28 15:34:06 +01:00
sparc	cmake: sparc: update sparc SoC to use SOC_LINKER_SCRIPT variable	2023-11-03 11:01:23 +01:00
x86	cmake: x86: update x86 SoC to use SOC_LINKER_SCRIPT variable	2023-11-03 11:01:23 +01:00
xtensa	soc: xtensa: adsp: add support for NXP ADSP for i.MX8ULP	2023-12-04 16:41:00 +00:00
CMakeLists.txt	…
Kconfig	…