69 lines
1.9 KiB
Plaintext
69 lines
1.9 KiB
Plaintext
# Intel CAVS SoC family configuration options
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#
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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_INTEL_ADSP
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select WINSTREAM
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bool
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if SOC_FAMILY_INTEL_ADSP
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config SOC_FAMILY
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string
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default "intel_adsp"
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config HP_SRAM_RESERVE
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int "Bytes to reserve at start of HP-SRAM"
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default 65536
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help
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Bytes to reserve at the start of HP-SRAM. Zephyr will not
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place any symbols here, though the host windows have
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addresses here. The SOF application also makes direct use
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of this region, so be very careful changing this value.
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config ADSP_WIN0_OFFSET
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int "Byte offset of host window zero"
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default 16384
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help
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Offset of the first host shared memory window (used for the
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"firmware status register" at boot) within the reserved
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region at the start of HP-SRAM.
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config ADSP_WIN3_OFFSET
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int "Byte offset of host window three"
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default 40960
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help
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Offset of the fourth host shared memory window (used for
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printk/log output) within the reserved region at the start
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of HP-SRAM.
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config IMR_MANIFEST_ADDR
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hex "Address of boot manifest struct within IMR memory"
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default 0xb0032000
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help
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Address where the rimage manifest struct is placed upon
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boot. Must be synchronized between Zephyr's linkage, the
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hardware, ROM and rimage configuration. Don't touch except
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with great care.
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config IMR_DATA_ADDR
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hex "Address of bootloader .data section within IMR memory"
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default 0xb0039000
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help
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Location to place .data contents in IMR memory during
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bootloader linkage.
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config ADSP_TRACE_SIMCALL
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bool "Emit SIMCALL output in addition to window tracing"
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help
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When true, the trace_out layer will also use a SIMCALL
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instruction to emit the passed data to the standard output
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of an enclosing simulator process. All window contents will
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remain identical.
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# Select SoC Part No. and configuration options
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source "soc/xtensa/intel_adsp/*/Kconfig.soc"
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endif # SOC_FAMILY_INTEL_ADSP
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