zephyr/soc/intel/intel_adsp
Kai Vehmanen 81977f2bff drivers: dma: intel_adsp_hda: fix intel_adsp_hda_unused() check
The ringbuffer availability check is subject to race with regards to
update of BF (Buffer Full) and BNE (Buffer Not Empty) bits in DGCS
register, and status of RP (Read Position) and WP (Write Position).

Following sequence is observed without this patch when
calling dma_get_status() on multiple Intel ADSP platforms:

iter 154 pending 1536 RP 768 WP 768, BNE 1, BF 1
-> dma_reload for 384
iter 155 pending 1536 RP 1152 WP 1152, BNE 1, BF 1
-> dma_reload for 384
iter 156 pending 0 RP 0 WP 0, BNE 1, BF 0

Value of pending is not expected to go from 1536 to zero if only 384
bytes have been consumed via dma_reload() since last call to
dma_get_status().

Change the logic to read DGCS register later, after the WP and RP have
been already read, and only check the BNE bit if Read and Write
Positions are equal.

Link: https://github.com/thesofproject/sof/issues/9418
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Co-developed-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
2024-09-04 09:53:57 +02:00
..
ace intel_adsp: Add board definitions for adsp simulator 2024-08-28 16:35:55 -04:00
cavs arch: use same syntax for custom arch calls 2024-08-12 12:43:36 +02:00
common drivers: dma: intel_adsp_hda: fix intel_adsp_hda_unused() check 2024-09-04 09:53:57 +02:00
tools soc: intel_adsp: tools: improve cavstool.py winstream code 2024-06-15 14:21:02 +02:00
CMakeLists.txt
Kconfig intel_adsp: Add board definitions for adsp simulator 2024-08-28 16:35:55 -04:00
Kconfig.defconfig soc: intel_adsp: DCACHE_LINE_SIZE was not defined 2024-08-20 19:43:37 -04:00
Kconfig.soc
soc.yml intel_adsp: ace30: Bring up ACE 3.0 (PTL) 2024-06-04 13:40:04 +02:00