189 lines
4.6 KiB
Plaintext
189 lines
4.6 KiB
Plaintext
/*
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* Copyright (C) 2021 StarFive, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "starfive_jh7100_clk.dtsi"
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "sifive,freedom-u74-arty";
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model = "sifive,freedom-u74-arty";
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "starfive,fu74-g000";
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cpu@0 {
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clock-frequency = <0>;
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compatible = "starfive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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reg = <0>;
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riscv,isa = "rv64gc";
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starfive,itim = <&itim0>;
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status = "okay";
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tlb-split;
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cpu0intctrl: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@1 {
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clock-frequency = <0>;
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compatible = "starfive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&cachectrl>;
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reg = <1>;
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riscv,isa = "rv64gc";
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starfive,itim = <&itim1>;
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status = "okay";
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tlb-split;
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cpu1intctrl: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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ram0:memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x2 0x0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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#clock-cells = <1>;
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compatible = "starfive,freedom-u74-arty", "simple-bus";
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ranges;
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cachectrl: cache-controller@2010000 {
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <2048>;
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cache-size = <2097152>;
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cache-unified;
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compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
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interrupt-parent = <&plic>;
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interrupts = <128 1>, <131 1>, <129 1>, <130 1>;
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/*next-level-cache = <&L40 &L36>;*/
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reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
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reg-names = "control", "sideband";
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};
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itim0: itim@1808000 {
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compatible = "starfive,itim0";
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reg = <0x0 0x1808000 0x0 0x8000>;
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reg-names = "mem";
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};
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itim1: itim@1820000 {
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compatible = "starfive,itim0";
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reg = <0x0 0x1820000 0x0 0x8000>;
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reg-names = "mem";
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};
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clint: clint@2000000 {
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compatible = "starfive,jh7100-clint", "sifive,clint0";
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interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
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&cpu1intctrl 3 &cpu1intctrl 7>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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};
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plic: plic@c000000 {
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compatible = "sifive,plic-1.0.0";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9
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&cpu1intctrl 11 &cpu1intctrl 9 >;
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reg = <0x0 0x0c000000 0x0 0x04000000>;
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riscv,max-priority = <7>;
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riscv,ndev = <127>;
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};
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uart3: serial@12440000 {
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compatible = "ns16550", "snps,dw-apb-uart";
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interrupt-parent = <&plic>;
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interrupts = <73 1>;
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reg = <0x0 0x12440000 0x0 0x10000>;
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reg-shift = <2>;
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clocks = <&uartclk>, <&apb2clk>;
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clock-names = "baudclk", "apb_pclk";
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clock-frequency = <100000000>;
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current-speed = <115200>;
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status = "disabled";
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};
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uart2: serial@12430000 {
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compatible = "ns16550", "snps,dw-apb-uart";
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interrupt-parent = <&plic>;
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interrupts = <72 1>;
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reg = <0x0 0x12430000 0x0 0x10000>;
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reg-shift = <2>;
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clocks = <&uartclk>, <&apb2clk>;
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clock-names = "baudclk", "apb_pclk";
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clock-frequency = <100000000>;
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current-speed = <115200>;
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status = "disabled";
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};
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uart1: hs_serial@11880000 {
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compatible = "ns16550", "snps,dw-apb-uart";
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interrupt-parent = <&plic>;
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interrupts = <93 1>;
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reg = <0x0 0x11880000 0x0 0x10000>;
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reg-shift = <2>;
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clocks = <&hs_uartclk>, <&apb1clk>;
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clock-names = "baudclk","apb_pclk";
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clock-frequency = <74250000>;
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current-speed = <115200>;
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status = "disabled";
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};
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uart0: hs_serial@11870000 {
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compatible = "ns16550", "snps,dw-apb-uart";
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interrupt-parent = <&plic>;
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interrupts = <92 1>;
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reg = <0x0 0x11870000 0x0 0x10000>;
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reg-shift = <2>;
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clocks = <&hs_uartclk>, <&apb1clk>;
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clock-names = "baudclk", "apb_pclk";
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clock-frequency = <74250000>;
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current-speed = <115200>;
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status = "disabled";
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};
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};
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};
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