Sylvio Alves f099bcd497 hotfix: drivers: i2s: update esp32s3/c3 I2S dtsi ... I2S driver was merged after interrupt .dtsi was changed, causing CI to fail. This updates it accordingly. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>		2024-08-29 16:10:28 -04:00
..
andes	dts: bindings: add andestech,l2c	2024-04-22 09:19:27 -04:00
efinix	dts: riscv: Fix incorrect plic size	2024-07-02 22:21:17 -04:00
espressif	hotfix: drivers: i2s: update esp32s3/c3 I2S dtsi	2024-08-29 16:10:28 -04:00
gd	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
ite	drivers: pinctrl: ITE: Add a property configure pin current strength	2024-06-06 00:41:35 -07:00
lowrisc	dts: opentitan: update plic interrupt count to match spec	2024-03-22 09:23:46 +00:00
microchip	dts: mbox: add PolarFire SoC mailbox interface	2024-02-01 04:33:16 -05:00
niosv	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
nordic	dts: boards: Add nRF54L15 ENGA configuration	2024-08-29 12:02:35 +02:00
openisa	soc/openisa: enable the `C` extension	2024-07-03 15:06:14 -04:00
qemu	dts: set the `riscv,isa` property for virt-based targets	2024-05-15 09:30:23 +02:00
sifive	dts: sifive: Update SoC compats	2024-04-18 14:56:00 +02:00
starfive	dts: jh7110: fix memory definitions	2024-04-09 14:20:39 +02:00
telink	…
neorv32.dtsi	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
renode_riscv32_virt.dtsi	dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC	2024-01-08 12:35:10 +01:00
riscv32-litex-vexriscv.dtsi	drivers: watchdog: litex: add litex watchdog	2024-08-19 10:02:01 -04:00