138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
/*
|
|
* Copyright (c) 2014-2015 Wind River Systems, Inc.
|
|
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
|
* Copyright (c) 2018 Prevas A/S
|
|
* Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
/**
|
|
* @file
|
|
* @brief System/hardware module for fsl_frdm_k22f platform
|
|
*
|
|
* This module provides routines to initialize and support board-level
|
|
* hardware for the fsl_frdm_k22f platform.
|
|
*/
|
|
|
|
#include <zephyr/kernel.h>
|
|
#include <zephyr/device.h>
|
|
#include <zephyr/init.h>
|
|
#include <soc.h>
|
|
#include <zephyr/drivers/uart.h>
|
|
#include <fsl_common.h>
|
|
#include <fsl_clock.h>
|
|
#include <zephyr/arch/cpu.h>
|
|
#include <cmsis_core.h>
|
|
|
|
#define TIMESRC_OSCERCLK (2)
|
|
|
|
#define CLOCK_NODEID(clk) \
|
|
DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
|
|
|
|
#define CLOCK_DIVIDER(clk) \
|
|
DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
|
|
|
|
static const osc_config_t oscConfig = {
|
|
.freq = CONFIG_OSC_XTAL0_FREQ,
|
|
.capLoad = 0,
|
|
|
|
#if defined(CONFIG_OSC_EXTERNAL)
|
|
.workMode = kOSC_ModeExt,
|
|
#elif defined(CONFIG_OSC_LOW_POWER)
|
|
.workMode = kOSC_ModeOscLowPower,
|
|
#elif defined(CONFIG_OSC_HIGH_GAIN)
|
|
.workMode = kOSC_ModeOscHighGain,
|
|
#else
|
|
#error "An oscillator mode must be defined"
|
|
#endif
|
|
|
|
.oscerConfig = {
|
|
.enableMode = 0U, /* Disable external reference clock */
|
|
#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
|
|
.erclkDiv = 0U,
|
|
#endif
|
|
},
|
|
};
|
|
|
|
static const mcg_pll_config_t pll0Config = {
|
|
.enableMode = 0U,
|
|
.prdiv = CONFIG_MCG_PRDIV0,
|
|
.vdiv = CONFIG_MCG_VDIV0,
|
|
};
|
|
|
|
static const sim_clock_config_t simConfig = {
|
|
.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
|
|
.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
|
|
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
|
|
SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
|
|
SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
|
|
SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
|
|
};
|
|
|
|
/**
|
|
*
|
|
* @brief Initialize the system clock
|
|
*
|
|
* This routine will configure the multipurpose clock generator (MCG) to
|
|
* set up the system clock.
|
|
* The MCG has nine possible modes, including Stop mode. This routine assumes
|
|
* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
|
|
* It transitions through the FLL Bypassed External (FBE) and
|
|
* PLL Bypassed External (PBE) modes to get to the desired
|
|
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
|
|
* clock.
|
|
*
|
|
*/
|
|
static ALWAYS_INLINE void clock_init(void)
|
|
{
|
|
CLOCK_SetSimSafeDivs();
|
|
|
|
CLOCK_InitOsc0(&oscConfig);
|
|
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
|
|
|
|
|
|
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
|
|
CONFIG_MCG_FCRDIV);
|
|
|
|
/* Configure FLL external reference divider (FRDIV). */
|
|
CLOCK_SetFllExtRefDiv(0);
|
|
|
|
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
|
|
|
|
CLOCK_SetSimConfig(&simConfig);
|
|
|
|
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
|
|
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
|
|
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Perform basic hardware initialization
|
|
*
|
|
* Initialize the interrupt controller device drivers.
|
|
* Also initialize the timer device driver, if required.
|
|
*
|
|
* @return 0
|
|
*/
|
|
|
|
void soc_early_init_hook(void)
|
|
{
|
|
/* release I/O power hold to allow normal run state */
|
|
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
|
|
|
|
/* Initialize PLL/system clock to 120 MHz */
|
|
clock_init();
|
|
}
|
|
|
|
#ifdef CONFIG_SOC_RESET_HOOK
|
|
|
|
void soc_reset_hook(void)
|
|
{
|
|
SystemInit();
|
|
}
|
|
|
|
#endif /* CONFIG_SOC_RESET_HOOK */
|