78 lines
1.8 KiB
Plaintext
78 lines
1.8 KiB
Plaintext
/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f0/stm32f051.dtsi>
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/ {
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clocks {
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clk_hsi48: clk-hsi48 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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status = "disabled";
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};
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};
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soc {
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compatible = "st,stm32f071", "st,stm32f0", "simple-bus";
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flash-controller@40022000 {
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flash0: flash@8000000 {
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erase-block-size = <2048>;
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};
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};
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pinctrl: pin-controller@48000000 {
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gpioe: gpio@48001000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
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};
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};
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/*
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* USARTs 3-4 share the same IRQ on stm32f071xx devices. This
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* configuration is not currently supported, so at most one of
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* these may be enabled at a time. Enabling more than one will
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* result in a build failure.
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*/
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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resets = <&rctl STM32_RESET(APB1, 18U)>;
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interrupts = <29 0>;
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status = "disabled";
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};
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usart4: serial@40004c00 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1, 19U)>;
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interrupts = <29 0>;
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status = "disabled";
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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resets = <&rctl STM32_RESET(APB1, 5U)>;
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interrupts = <18 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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};
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dma1: dma@40020000 {
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interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
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};
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};
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};
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