zephyr/dts/arm/st/f0
Fabrice DJIATSA 9e4c554487 dts: arm: st: remove clock node from parent node soc
Since the clock node is not a child node of the soc node,
but from the root node.
This removes the warning log at compilation.


Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2024-08-26 11:05:00 -04:00
..
stm32f0.dtsi dts: arm: stm32 mcu disable the iwdg node in the dtsi 2024-08-01 09:11:01 +01:00
stm32f030.dtsi
stm32f030X4.dtsi
stm32f030X6.dtsi
stm32f030X8.dtsi
stm32f030Xc.dtsi
stm32f031.dtsi
stm32f031X6.dtsi
stm32f042.dtsi dts: arm: st: remove clock node from parent node soc 2024-08-26 11:05:00 -04:00
stm32f042X6.dtsi
stm32f051.dtsi
stm32f051X8.dtsi
stm32f070.dtsi
stm32f070Xb.dtsi
stm32f071.dtsi hwmv2: Introduce Hardware model version 2 and convert devices 2024-03-02 16:56:33 -05:00
stm32f072.dtsi dts: bindings: can: remove optional sample point properties 2024-03-17 15:36:19 +01:00
stm32f072X8.dtsi
stm32f072Xb.dtsi
stm32f091.dtsi dts: bindings: can: remove optional sample point properties 2024-03-17 15:36:19 +01:00
stm32f091Xc.dtsi
stm32f098Xc.dtsi