182 lines
5.2 KiB
C
182 lines
5.2 KiB
C
/* loapic.h - public LOAPIC APIs */
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/*
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* Copyright (c) 2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_LOAPIC_H_
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#define ZEPHYR_INCLUDE_DRIVERS_LOAPIC_H_
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#include <arch/cpu.h>
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#include <arch/x86/msr.h>
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/* Local APIC Register Offset */
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#define LOAPIC_ID 0x020 /* Local APIC ID Reg */
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#define LOAPIC_VER 0x030 /* Local APIC Version Reg */
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#define LOAPIC_TPR 0x080 /* Task Priority Reg */
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#define LOAPIC_APR 0x090 /* Arbitration Priority Reg */
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#define LOAPIC_PPR 0x0a0 /* Processor Priority Reg */
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#define LOAPIC_EOI 0x0b0 /* EOI Reg */
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#define LOAPIC_LDR 0x0d0 /* Logical Destination Reg */
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#define LOAPIC_DFR 0x0e0 /* Destination Format Reg */
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#define LOAPIC_SVR 0x0f0 /* Spurious Interrupt Reg */
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#define LOAPIC_ISR 0x100 /* In-service Reg */
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#define LOAPIC_TMR 0x180 /* Trigger Mode Reg */
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#define LOAPIC_IRR 0x200 /* Interrupt Request Reg */
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#define LOAPIC_ESR 0x280 /* Error Status Reg */
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#define LOAPIC_ICRLO 0x300 /* Interrupt Command Reg */
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#define LOAPIC_ICRHI 0x310 /* Interrupt Command Reg */
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#define LOAPIC_TIMER 0x320 /* LVT (Timer) */
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#define LOAPIC_THERMAL 0x330 /* LVT (Thermal) */
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#define LOAPIC_PMC 0x340 /* LVT (PMC) */
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#define LOAPIC_LINT0 0x350 /* LVT (LINT0) */
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#define LOAPIC_LINT1 0x360 /* LVT (LINT1) */
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#define LOAPIC_ERROR 0x370 /* LVT (ERROR) */
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#define LOAPIC_TIMER 0x320 /* LVT (Timer) */
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#define LOAPIC_TIMER_ICR 0x380 /* Timer Initial Count Reg */
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#define LOAPIC_TIMER_CCR 0x390 /* Timer Current Count Reg */
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#define LOAPIC_TIMER_CONFIG 0x3e0 /* Timer Divide Config Reg */
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#define LOAPIC_ICR_BUSY 0x00001000 /* delivery status: 1 = busy */
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#define LOAPIC_ICR_IPI_OTHERS 0x000C4000U /* normal IPI to other CPUs */
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#define LOAPIC_ICR_IPI_INIT 0x00004500U
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#define LOAPIC_ICR_IPI_STARTUP 0x00004600U
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#define LOAPIC_LVT_MASKED 0x00010000 /* mask */
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#ifndef _ASMLANGUAGE
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void z_loapic_enable(unsigned char cpu_number);
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extern void z_loapic_int_vec_set(unsigned int irq, unsigned int vector);
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extern void z_loapic_irq_enable(unsigned int irq);
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extern void z_loapic_irq_disable(unsigned int irq);
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/**
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* @brief Read 64-bit value from the local APIC in x2APIC mode.
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*
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* @param reg the LOAPIC register number to read (LOAPIC_*)
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*/
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static inline u64_t x86_read_x2apic(unsigned int reg)
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{
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reg >>= 4;
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return z_x86_msr_read(X86_X2APIC_BASE_MSR + reg);
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}
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/**
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* @brief Read 32-bit value from the local APIC in xAPIC (MMIO) mode.
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*
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* @param reg the LOAPIC register number to read (LOAPIC_*)
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*/
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static inline u32_t x86_read_xapic(unsigned int reg)
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{
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return sys_read32(CONFIG_LOAPIC_BASE_ADDRESS + reg);
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}
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/**
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* @brief Read value from the local APIC using the default mode.
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*
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* Returns a 32-bit value read from the local APIC, using the access
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* method determined by CONFIG_X2APIC (either xAPIC or x2APIC). Note
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* that 64-bit reads are only allowed in x2APIC mode and can only be
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* done by calling x86_read_x2apic() directly. (This is intentional.)
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*
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* @param reg the LOAPIC register number to read (LOAPIC_*)
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*/
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static inline u32_t x86_read_loapic(unsigned int reg)
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{
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#ifdef CONFIG_X2APIC
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return x86_read_x2apic(reg);
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#else
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return x86_read_xapic(reg);
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#endif
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}
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/**
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* @brief Write 64-bit value to the local APIC in x2APIC mode.
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*
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* @param reg the LOAPIC register number to write (one of LOAPIC_*)
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* @param val 64-bit value to write
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*/
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static inline void x86_write_x2apic(unsigned int reg, u64_t val)
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{
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reg >>= 4;
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z_x86_msr_write(X86_X2APIC_BASE_MSR + reg, val);
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}
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/**
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* @brief Write 32-bit value to the local APIC in xAPIC (MMIO) mode.
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*
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* @param reg the LOAPIC register number to write (one of LOAPIC_*)
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* @param val 32-bit value to write
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*/
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static inline void x86_write_xapic(unsigned int reg, u32_t val)
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{
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sys_write32(val, CONFIG_LOAPIC_BASE_ADDRESS + reg);
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}
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/**
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* @brief Write 32-bit value to the local APIC using the default mode.
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*
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* Write a 32-bit value to the local APIC, using the access method
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* determined by CONFIG_X2APIC (either xAPIC or x2APIC). Note that
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* 64-bit writes are only available in x2APIC mode and can only be
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* done by calling x86_write_x2apic() directly. (This is intentional.)
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*
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* @param reg the LOAPIC register number to write (one of LOAPIC_*)
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* @param val 32-bit value to write
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*/
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static inline void x86_write_loapic(unsigned int reg, u32_t val)
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{
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#ifdef CONFIG_X2APIC
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x86_write_x2apic(reg, val);
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#else
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x86_write_xapic(reg, val);
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#endif
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}
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/**
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* @brief Send an IPI.
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*
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* @param apic_id If applicable, the target CPU APIC ID (0 otherwise).
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* @param ipi Type of IPI: one of the LOAPIC_ICR_IPI_* constants.
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* @param vector If applicable, the target vector (0 otherwise).
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*/
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static inline void z_loapic_ipi(u8_t apic_id, u32_t ipi, u8_t vector)
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{
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ipi |= vector;
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#ifndef CONFIG_X2APIC
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/*
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* Legacy xAPIC mode: first wait for any previous IPI to be delivered.
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*/
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while (x86_read_xapic(LOAPIC_ICRLO) & LOAPIC_ICR_BUSY) {
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}
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x86_write_xapic(LOAPIC_ICRHI, apic_id << 24);
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x86_write_xapic(LOAPIC_ICRLO, ipi);
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#else
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/*
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* x2APIC mode is greatly simplified: one write, no delivery status.
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*/
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x86_write_x2apic(LOAPIC_ICRLO, (((u64_t) apic_id) << 32) | ipi);
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#endif
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_DRIVERS_LOAPIC_H_ */
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