When CONFIG_RISCV_VECTORED_MODE is disabled, CLIC claims interrupts using
CSR 'mnxti' and handles all pending interrupts before exiting the ISR.
When CONFIG_RISCV_VECTORED_MODE is enabled, all interrupts use vector mode
and are claimed automatically. The RISC-V common ISR is used for interrupts
hooked into SW ISR table, but it only handle one pending interrupt per ISR.
This commit enhances CLIC to set vector mode for direct ISRs only and use
the CLIC common entry for regular ISRs to handles multiple pending
interrupts in an ISR.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
