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style: drivers: comply with MISRA C:2012 Rule 15.6 

Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit is contained in:
Pisit Sawangvonganan 2024-08-16 13:26:13 +07:00 committed by Henrik Brix Andersen
parent 535b854d87
commit 1bcae0ea9f
56 changed files with 247 additions and 131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/adc/adc_rpi_pico.c
View File

@ -91,8 +91,9 @@ static inline void adc_clear_errors(void)
static inline void adc_enable(void)
{
adc_hw->cs = ADC_CS_EN_BITS;
while (!(adc_hw->cs & ADC_CS_READY_BITS))
while (!(adc_hw->cs & ADC_CS_READY_BITS)) {
;
}
}
static int adc_rpi_channel_setup(const struct device *dev,

3
drivers/adc/adc_smartbond_sdadc.c
View File

@ -150,8 +150,9 @@ static void adc_context_start_sampling(struct adc_context *ctx)
int current_channel = u32_count_trailing_zeros(data->channel_read_mask);
/* Wait until the SDADC LDO stabilizes */
while (!(SDADC->SDADC_CTRL_REG & SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk))
while (!(SDADC->SDADC_CTRL_REG & SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk)) {
__NOP();
}
if (ctx->sequence.calibrate) {
/* TODO: Add calibration code */

3
drivers/clock_control/clock_control_npcx.c
View File

@ -223,8 +223,9 @@ static int npcx_clock_control_init(const struct device *dev)
/* Load M and N values into the frequency multiplier */
inst_cdcg->HFCGCTRL |= BIT(NPCX_HFCGCTRL_LOAD);
/* Wait for stable */
while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
while (IS_BIT_SET(inst_cdcg->HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG)) {
;
}
}
/* Set all clock prescalers of core and peripherals. */

3
drivers/counter/counter_gecko_stimer.c
View File

@ -110,8 +110,9 @@ static int counter_gecko_start(const struct device *dev)
bool is_top_timer_running = false;
error_code = sl_sleeptimer_is_timer_running(&top_timer, &is_top_timer_running);
if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true))
if ((error_code == SL_STATUS_OK) && (is_top_timer_running == true)) {
return 0;
}
struct counter_gecko_data *const dev_data = (struct counter_gecko_data *const)(dev)->data;
error_code = sl_sleeptimer_start_timer(&top_timer, dev_data->top_data.ticks, top_callback,

3
drivers/counter/counter_native_posix.c
View File

@ -181,8 +181,9 @@ static int ctr_set_alarm(const struct device *dev, uint8_t chan_id,
{
ARG_UNUSED(dev);
if (is_alarm_pending[chan_id])
if (is_alarm_pending[chan_id]) {
return -EBUSY;
}
uint32_t ticks = alarm_cfg->ticks;

29
drivers/dai/intel/dmic/dmic.c
View File

@ -76,11 +76,13 @@ static int32_t exp_fixed(int32_t x)
int i;
int n = 0;
if (x < Q_CONVERT_FLOAT(-11.5, 27))
if (x < Q_CONVERT_FLOAT(-11.5, 27)) {
return 0;
}
if (x > Q_CONVERT_FLOAT(7.6245, 27))
if (x > Q_CONVERT_FLOAT(7.6245, 27)) {
return INT32_MAX;
}
/* x is Q5.27 */
xs = x;
@ -94,8 +96,9 @@ static int32_t exp_fixed(int32_t x)
*/
z = Q_SHIFT_RND(exp_small_fixed(Q_SHIFT_LEFT(xs, 27, 29)), 23, 20);
y = ONE_Q20;
for (i = 0; i < (1 << n); i++)
for (i = 0; i < (1 << n); i++) {
y = (int32_t)Q_MULTSR_32X32((int64_t)y, z, 20, 20, 20);
}
return y;
}
@ -104,8 +107,9 @@ static int32_t db2lin_fixed(int32_t db)
{
int32_t arg;
if (db < Q_CONVERT_FLOAT(-100.0, 24))
if (db < Q_CONVERT_FLOAT(-100.0, 24)) {
return 0;
}
/* Q8.24 x Q5.27, result needs to be Q5.27 */
arg = (int32_t)Q_MULTSR_32X32((int64_t)db, LOG10_DIV20_Q27, 24, 27, 27);
@ -383,8 +387,9 @@ static int dai_dmic_remove(struct dai_intel_dmic *dmic)
* Note: dai_put() function that calls remove() applies the spinlock
* so it is not needed here to protect access to mask bits.
*/
if (active_fifos_mask || pause_mask)
if (active_fifos_mask || pause_mask) {
return 0;
}
/* Disable DMIC clock and power */
dai_dmic_en_clk_gating(dmic);
@ -442,8 +447,9 @@ static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *c
/* Read SSP timestamp registers */
ntk = sys_read32(tsctrl) & TS_LOCAL_TSCTRL_NTK;
if (!ntk)
if (!ntk) {
goto out;
}
/* NTK was set, get wall clock */
tsd->walclk = sys_read64(TS_DMIC_LOCAL_WALCLK);
@ -456,8 +462,9 @@ static int dai_timestamp_dmic_get(const struct device *dev, struct dai_ts_cfg *c
out:
tsd->walclk_rate = cfg->walclk_rate;
if (!ntk)
if (!ntk) {
return -ENODATA;
}
return 0;
}
@ -484,8 +491,9 @@ static void dai_dmic_gain_ramp(struct dai_intel_dmic *dmic)
* task associated with each DAI, so we don't need to hold the lock to
* read the value here.
*/
if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11)
if (dmic->gain == DMIC_HW_FIR_GAIN_MAX << 11) {
return;
}
key = k_spin_lock(&dmic->lock);
@ -659,10 +667,11 @@ static void dai_dmic_stop(struct dai_intel_dmic *dmic, bool stop_is_pause)
* If stop is not for pausing, it is safe to clear the pause bit.
*/
dai_dmic_global.active_fifos_mask &= ~BIT(dmic->dai_config_params.dai_index);
if (stop_is_pause)
if (stop_is_pause) {
dai_dmic_global.pause_mask |= BIT(dmic->dai_config_params.dai_index);
else
} else {
dai_dmic_global.pause_mask &= ~BIT(dmic->dai_config_params.dai_index);
}
for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
/* Don't stop CIC yet if one FIFO remains active */

6
drivers/dai/intel/dmic/dmic.h
View File

@ -205,11 +205,13 @@ static inline int dmic_get_unmute_ramp_from_samplerate(int rate)
time_ms = Q_MULTSR_32X32((int32_t)rate, LOGRAMP_TIME_COEF_Q15, 0, 15, 0) +
LOGRAMP_TIME_OFFS_Q0;
if (time_ms > LOGRAMP_TIME_MAX_MS)
if (time_ms > LOGRAMP_TIME_MAX_MS) {
return LOGRAMP_TIME_MAX_MS;
}
if (time_ms < LOGRAMP_TIME_MIN_MS)
if (time_ms < LOGRAMP_TIME_MIN_MS) {
return LOGRAMP_TIME_MIN_MS;
}
return time_ms;
}

9
drivers/dai/intel/dmic/dmic_nhlt.c
View File

@ -668,8 +668,9 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
/* Configure clock source */
ret = dai_dmic_set_clock(dmic, dmic_cfg->clock_source);
if (ret)
if (ret) {
return ret;
}
/* Get OUTCONTROLx configuration */
if (num_fifos < 1 || num_fifos > DMIC_HW_FIFOS_MAX) {
@ -678,8 +679,9 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
}
for (n = 0; n < DMIC_HW_FIFOS_MAX; n++) {
if (!(channel_ctrl_mask & (1 << n)))
if (!(channel_ctrl_mask & (1 << n))) {
continue;
}
val = *(uint32_t *)p;
ret = print_outcontrol(val);
@ -802,8 +804,9 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
#else
ret = dai_nhlt_dmic_dai_params_get(dmic);
#endif
if (ret)
if (ret) {
return ret;
}
LOG_INF("dmic_set_config_nhlt(): enable0 %u, enable1 %u",
dmic->enable[0], dmic->enable[1]);

10
drivers/dai/intel/hda/hda.c
View File

@ -32,10 +32,13 @@ static int dai_hda_set_config_tplg(struct dai_intel_hda *dp, const void *spec_co
struct dai_intel_hda_pdata *hda = dai_get_drvdata(dp);
const struct dai_intel_ipc_hda_params *config = spec_config;
if (config->channels)
if (config->channels) {
hda->params.channels = config->channels;
if (config->rate)
}
if (config->rate) {
hda->params.rate = config->rate;
}
return 0;
}
@ -65,8 +68,9 @@ static int dai_hda_config_set(const struct device *dev, const struct dai_config
{
struct dai_intel_hda *dp = (struct dai_intel_hda *)dev->data;
if (cfg->type == DAI_INTEL_HDA)
if (cfg->type == DAI_INTEL_HDA) {
return dai_hda_set_config_tplg(dp, bespoke_cfg);
}
return 0;
}

12
drivers/dai/intel/ssp/ssp.c
View File

@ -1999,8 +1999,9 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con
aux_len = cfg_len - pre_aux_len;
aux_ptr = (uint8_t *)blob + pre_aux_len;
if (aux_len <= 0)
if (aux_len <= 0) {
return 0;
}
return dai_ssp_parse_tlv(dp, aux_ptr, aux_len);
}
@ -2132,17 +2133,20 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co
if (blob15->version == SSP_BLOB_VER_1_5) {
err = dai_ssp_parse_aux_data(dp, spec_config);
if (err)
if (err) {
return err;
}
dai_ssp_set_reg_config(dp, cfg, &blob15->i2s_ssp_config);
err = dai_ssp_set_clock_control_ver_1_5(dp, &blob15->i2s_mclk_control);
if (err)
if (err) {
return err;
}
} else {
dai_ssp_set_reg_config(dp, cfg, &blob->i2s_driver_config.i2s_config);
err = dai_ssp_set_clock_control_ver_1(dp, &blob->i2s_driver_config.mclk_config);
if (err)
if (err) {
return err;
}
}
ssp_plat_data->clk_active |= SSP_CLK_MCLK_ES_REQ;

3
drivers/dma/dma_dw_common.c
View File

@ -565,8 +565,9 @@ int dw_dma_stop(const struct device *dev, uint32_t channel)
* needed
*/
ret = pm_device_state_get(dev, &pm_state);
if (!ret && pm_state != PM_DEVICE_STATE_ACTIVE)
if (!ret && pm_state != PM_DEVICE_STATE_ACTIVE) {
goto out;
}
if (!dw_dma_is_enabled(dev, channel) && chan_data->state != DW_DMA_SUSPENDED) {
ret = 0;

48
drivers/espi/espi_npcx.c
View File

@ -208,8 +208,9 @@ static void espi_init_wui_callback(const struct device *dev,
miwu_dev_callback_handler_t handler)
{
/* VW signal which has no wake-up input source */
if (wui->table == NPCX_MIWU_TABLE_NONE)
if (wui->table == NPCX_MIWU_TABLE_NONE) {
return;
}
/* Install callback function */
npcx_miwu_init_dev_callback(callback, wui, handler, dev);
@ -468,8 +469,9 @@ static void espi_vw_config_input(const struct device *dev,
/* IE & WE bits are already set? */
if (IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_IE) &&
IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE))
IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE)) {
return;
}
/* Set IE & WE bits in VWEVMS */
inst->VWEVMS[idx] |= BIT(NPCX_VWEVMS_IE) | BIT(NPCX_VWEVMS_WE);
@ -699,17 +701,21 @@ static int espi_npcx_configure(const struct device *dev, struct espi_cfg *cfg)
}
/* Configure eSPI supported channels */
if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL)
if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
inst->ESPICFG |= BIT(NPCX_ESPICFG_PCCHN_SUPP);
}
if (cfg->channel_caps & ESPI_CHANNEL_VWIRE)
if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) {
inst->ESPICFG |= BIT(NPCX_ESPICFG_VWCHN_SUPP);
}
if (cfg->channel_caps & ESPI_CHANNEL_OOB)
if (cfg->channel_caps & ESPI_CHANNEL_OOB) {
inst->ESPICFG |= BIT(NPCX_ESPICFG_OOBCHN_SUPP);
}
if (cfg->channel_caps & ESPI_CHANNEL_FLASH)
if (cfg->channel_caps & ESPI_CHANNEL_FLASH) {
inst->ESPICFG |= BIT(NPCX_ESPICFG_FLASHCHN_SUPP);
}
LOG_DBG("%s: %d %d ESPICFG: 0x%08X", __func__,
max_freq, io_mode, inst->ESPICFG);
@ -769,9 +775,11 @@ static int espi_npcx_send_vwire(const struct device *dev,
}
/* Find signal in VW output table */
for (sig_idx = 0; sig_idx < vw_tbl_size; sig_idx++)
if (vw_tbl[sig_idx].sig == signal)
for (sig_idx = 0; sig_idx < vw_tbl_size; sig_idx++) {
if (vw_tbl[sig_idx].sig == signal) {
break;
}
}
if (sig_idx == vw_tbl_size) {
LOG_ERR("%s signal %d is invalid", __func__, signal);
@ -814,7 +822,7 @@ static int espi_npcx_receive_vwire(const struct device *dev,
uint8_t reg_idx, bitmask, sig_idx, val;
/* Find signal in VW input table */
for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_in_tbl); sig_idx++)
for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_in_tbl); sig_idx++) {
if (vw_in_tbl[sig_idx].sig == signal) {
reg_idx = vw_in_tbl[sig_idx].reg_idx;
bitmask = vw_in_tbl[sig_idx].bitmask;
@ -827,9 +835,10 @@ static int espi_npcx_receive_vwire(const struct device *dev,
*level = !!(val & bitmask);
return 0;
}
}
/* Find signal in VW output table */
for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_out_tbl); sig_idx++)
for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_out_tbl); sig_idx++) {
if (vw_out_tbl[sig_idx].sig == signal) {
reg_idx = vw_out_tbl[sig_idx].reg_idx;
bitmask = vw_out_tbl[sig_idx].bitmask;
@ -841,6 +850,7 @@ static int espi_npcx_receive_vwire(const struct device *dev,
*level = !!(val & bitmask);
return 0;
}
}
LOG_ERR("%s Out of index %d", __func__, signal);
return -EIO;
@ -921,8 +931,9 @@ static int espi_npcx_send_oob(const struct device *dev,
int i;
oob_data = 0;
for (i = 0; i < sz_oob_tx % 4; i++)
for (i = 0; i < sz_oob_tx % 4; i++) {
oob_data |= (oob_buf[i] << (8 * i));
}
inst->OOBTXBUF[idx_tx_buf + 1] = oob_data;
}
@ -934,8 +945,9 @@ static int espi_npcx_send_oob(const struct device *dev,
oob_data |= BIT(NPCX_OOBCTL_OOB_AVAIL);
inst->OOBCTL = oob_data;
while (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL))
while (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL)) {
;
}
LOG_DBG("%s issued!!", __func__);
return 0;
@ -1004,8 +1016,9 @@ static int espi_npcx_receive_oob(const struct device *dev,
int i;
oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
for (i = 0; i < sz_oob_rx % 4; i++)
for (i = 0; i < sz_oob_rx % 4; i++) {
*(oob_buf++) = (oob_data >> (8 * i)) & 0xFF;
}
}
/* Notify host that OOB received buffer is free now. */
@ -1365,12 +1378,14 @@ static int espi_npcx_init(const struct device *dev)
#endif
/* Configure Virtual Wire input signals */
for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++)
for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++) {
espi_vw_config_input(dev, &vw_in_tbl[i]);
}
/* Configure Virtual Wire output signals */
for (i = 0; i < ARRAY_SIZE(vw_out_tbl); i++)
for (i = 0; i < ARRAY_SIZE(vw_out_tbl); i++) {
espi_vw_config_output(dev, &vw_out_tbl[i]);
}
/* Configure Virtual Wire GPIOs that are output high at reset state */
for (i = 0; i < ARRAY_SIZE(vw_out_gpio_tbl1); i++) {
@ -1378,9 +1393,10 @@ static int espi_npcx_init(const struct device *dev)
}
/* Configure wake-up input and callback for eSPI VW input signal */
for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++)
for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++) {
espi_init_wui_callback(dev, &vw_in_callback[i],
&vw_in_tbl[i].vw_wui, espi_vw_generic_isr);
}
/* Configure wake-up input and callback for ESPI_RST signal */
espi_init_wui_callback(dev, &espi_rst_callback,

3
drivers/ethernet/eth_adin2111.c
View File

@ -1061,8 +1061,9 @@ static int eth_adin2111_find_filter(const struct device *dev, uint8_t *mac, cons
}
if ((reg & UINT16_MAX) == sys_get_be16(&mac[0])) {
if ((port_idx == 0 && !(reg & ADIN2111_ADDR_APPLY2PORT1)) ||
(port_idx == 1 && !(reg & ADIN2111_ADDR_APPLY2PORT2)))
(port_idx == 1 && !(reg & ADIN2111_ADDR_APPLY2PORT2))) {
continue;
}
ret = eth_adin2111_reg_read(dev, ADIN2111_ADDR_FILT_LWR + offset, &reg);
if (ret < 0) {

3
drivers/ethernet/eth_ivshmem_queue.c
View File

@ -82,8 +82,9 @@ void eth_ivshmem_queue_reset(struct eth_ivshmem_queue *q)
memset(q->tx.shmem, 0, q->vring_header_size);
/* Init TX ring descriptors */
for (unsigned int i = 0; i < q->tx.vring.num - 1; i++)
for (unsigned int i = 0; i < q->tx.vring.num - 1; i++) {
q->tx.vring.desc[i].next = i + 1;
}
q->tx.vring.desc[q->tx.vring.num - 1].next = 0;
}

3
drivers/ethernet/eth_lan865x.c
View File

@ -368,8 +368,9 @@ static int lan865x_default_config(const struct device *dev, uint8_t silicon_rev)
lan865x_set_specific_multicast_addr(dev);
ret = lan865x_init_chip(dev, silicon_rev);
if (ret < 0)
if (ret < 0) {
return ret;
}
if (cfg->plca->enable) {
ret = lan865x_config_plca(dev, cfg->plca->node_id,

6
drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c
View File

@ -294,8 +294,9 @@ static inline int enet_qos_dma_reset(enet_qos_t *base)
if (CONFIG_ETH_NXP_ENET_QOS_DMA_RESET_WAIT_TIME == 0) {
/* spin and wait forever for the reset flag to clear */
while (ENET_QOS_REG_GET(DMA_MODE, SWR, base->DMA_MODE))
while (ENET_QOS_REG_GET(DMA_MODE, SWR, base->DMA_MODE)) {
;
}
goto done;
}
@ -340,8 +341,9 @@ static inline void enet_qos_mtl_config_init(enet_qos_t *base)
/* Wait for flush to finish */
while (ENET_QOS_REG_GET(MTL_QUEUE_MTL_TXQX_OP_MODE, FTQ,
base->MTL_QUEUE[0].MTL_TXQX_OP_MODE))
base->MTL_QUEUE[0].MTL_TXQX_OP_MODE)) {
;
}
/* Enable only Transmit Queue 0 (optimization/configuration pending) with maximum size */
base->MTL_QUEUE[0].MTL_TXQX_OP_MODE =

3
drivers/ethernet/eth_smsc91x.c
View File

@ -99,8 +99,9 @@ static ALWAYS_INLINE unsigned int smsc_current_bank(struct smsc_data *sc)
static void smsc_mmu_wait(struct smsc_data *sc)
{
__ASSERT((smsc_current_bank(sc) == 2), "%s called when not in bank 2", __func__);
while (sys_read16(sc->smsc_reg + MMUCR) & MMUCR_BUSY)
while (sys_read16(sc->smsc_reg + MMUCR) & MMUCR_BUSY) {
;
}
}
static ALWAYS_INLINE uint8_t smsc_read_1(struct smsc_data *sc, int offset)

3
drivers/ethernet/nxp_enet/eth_nxp_enet.c
View File

@ -620,8 +620,9 @@ static inline void nxp_enet_unique_mac(uint8_t *mac_addr)
{
uint32_t id = ETH_NXP_ENET_UNIQUE_ID;
if (id == 0xFFFFFF)
if (id == 0xFFFFFF) {
LOG_ERR("No unique MAC can be provided in this platform");
}
/* Setting LAA bit because it is not guaranteed universally unique */
mac_addr[0] = FREESCALE_OUI_B0 | 0x02;

21
drivers/flash/flash_cadence_qspi_nor_ll.c
View File

@ -133,8 +133,9 @@ int cad_qspi_stig_cmd_helper(struct cad_qspi_params *cad_params, int cs, uint32_
do {
uint32_t reg = sys_read32(cad_params->reg_base + CAD_QSPI_FLASHCMD);
if (!(reg & CAD_QSPI_FLASHCMD_EXECUTE_STAT))
if (!(reg & CAD_QSPI_FLASHCMD_EXECUTE_STAT)) {
break;
}
count++;
} while (count < CAD_QSPI_COMMAND_TIMEOUT);
@ -172,8 +173,9 @@ int cad_qspi_stig_read_cmd(struct cad_qspi_params *cad_params, uint32_t opcode,
return -1;
}
if ((num_bytes > 8) || (num_bytes == 0))
if ((num_bytes > 8) || (num_bytes == 0)) {
return -1;
}
if (cad_params == NULL) {
LOG_ERR("Wrong parameter\n");
@ -208,8 +210,9 @@ int cad_qspi_stig_wr_cmd(struct cad_qspi_params *cad_params, uint32_t opcode, ui
return -1;
}
if ((num_bytes > 8) || (num_bytes == 0))
if ((num_bytes > 8) || (num_bytes == 0)) {
return -1;
}
if (cad_params == NULL) {
LOG_ERR("Wrong parameter\n");
@ -225,8 +228,9 @@ int cad_qspi_stig_wr_cmd(struct cad_qspi_params *cad_params, uint32_t opcode, ui
sys_write32(input[0], cad_params->reg_base + CAD_QSPI_FLASHCMD_WRDATA0);
if (num_bytes > 4)
if (num_bytes > 4) {
sys_write32(input[1], cad_params->reg_base + CAD_QSPI_FLASHCMD_WRDATA1);
}
return cad_qspi_stig_cmd_helper(cad_params, cad_params->cad_qspi_cs, cmd);
}
@ -236,8 +240,9 @@ int cad_qspi_stig_addr_cmd(struct cad_qspi_params *cad_params, uint32_t opcode,
{
uint32_t cmd;
if (dummy > ((1 << CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES_MAX) - 1))
if (dummy > ((1 << CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES_MAX) - 1)) {
return -1;
}
if (cad_params == NULL) {
LOG_ERR("Wrong parameter\n");
@ -576,11 +581,13 @@ int cad_qspi_int_disable(struct cad_qspi_params *cad_params, uint32_t mask)
return -EINVAL;
}
if (cad_qspi_idle(cad_params) == 0)
if (cad_qspi_idle(cad_params) == 0) {
return -1;
}
if ((CAD_QSPI_INT_STATUS_ALL & mask) == 0)
if ((CAD_QSPI_INT_STATUS_ALL & mask) == 0) {
return -1;
}
sys_write32(mask, cad_params->reg_base + CAD_QSPI_IRQMSK);
return 0;

10
drivers/flash/flash_mspi_atxp032.c
View File

@ -180,13 +180,14 @@ static void acquire(const struct device *flash)
if (cfg->sw_multi_periph) {
while (mspi_dev_config(cfg->bus, &cfg->dev_id,
MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg))
MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg)) {
;
}
} else {
while (mspi_dev_config(cfg->bus, &cfg->dev_id,
MSPI_DEVICE_CONFIG_NONE, NULL))
MSPI_DEVICE_CONFIG_NONE, NULL)) {
;
}
}
}
@ -195,8 +196,9 @@ static void release(const struct device *flash)
const struct flash_mspi_atxp032_config *cfg = flash->config;
struct flash_mspi_atxp032_data *data = flash->data;
while (mspi_get_channel_status(cfg->bus, cfg->port))
while (mspi_get_channel_status(cfg->bus, cfg->port)) {
;
}
k_sem_give(&data->lock);
}

7
drivers/flash/flash_mspi_emul_device.c
View File

@ -63,13 +63,14 @@ static void acquire(const struct device *flash)
k_sem_take(&data->lock, K_FOREVER);
if (cfg->sw_multi_periph) {
while (mspi_dev_config(data->bus, &cfg->dev_id,
MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg))
MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg)) {
;
}
} else {
while (mspi_dev_config(data->bus, &cfg->dev_id,
MSPI_DEVICE_CONFIG_NONE, NULL))
MSPI_DEVICE_CONFIG_NONE, NULL)) {
;
}
}
}

6
drivers/flash/flash_rpi_pico.c
View File

@ -65,8 +65,9 @@ static uint8_t flash_ram_buffer[PAGE_SIZE];
static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void)
{
if (boot2_copyout_valid)
if (boot2_copyout_valid) {
return;
}
for (int i = 0; i < BOOT2_SIZE_WORDS; ++i)
boot2_copyout[i] = ((uint32_t *)FLASH_BASE)[i];
__compiler_memory_barrier();
@ -124,8 +125,9 @@ void __no_inline_not_in_flash_func(flash_put_get)(const uint8_t *tx, uint8_t *rx
}
}
if (!did_something && __builtin_expect(flash_was_aborted(), 0))
if (!did_something && __builtin_expect(flash_was_aborted(), 0)) {
break;
}
}
flash_cs_force(OUTOVER_HIGH);
}

12
drivers/flash/soc_flash_cc13xx_cc26xx.c
View File

@ -43,8 +43,9 @@ static int flash_cc13xx_cc26xx_init(const struct device *dev)
static void flash_cc13xx_cc26xx_cache_restore(uint32_t vims_mode)
{
while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING)
while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING) {
;
}
/* Restore VIMS mode and line buffers */
if (vims_mode != VIMS_MODE_DISABLED) {
@ -61,8 +62,9 @@ static uint32_t flash_cc13xx_cc26xx_cache_disable(void)
/* VIMS and both line buffers should be off during flash update */
VIMSLineBufDisable(VIMS_BASE);
while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING)
while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING) {
;
}
/* Save current VIMS mode for restoring it later */
vims_mode = VIMSModeGet(VIMS_BASE);
@ -139,8 +141,9 @@ static int flash_cc13xx_cc26xx_erase(const struct device *dev, off_t offs,
/* Erase sector/page one by one, break out in case of an error */
cnt = size / FLASH_ERASE_SIZE;
for (i = 0; i < cnt; i++, offs += FLASH_ERASE_SIZE) {
while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY)
while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY) {
;
}
rc = FlashSectorErase(offs);
if (rc != FAPI_STATUS_SUCCESS) {
@ -200,8 +203,9 @@ static int flash_cc13xx_cc26xx_write(const struct device *dev, off_t offs,
key = irq_lock();
while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY)
while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY) {
;
}
rc = FlashProgram((uint8_t *)data, offs, size);
if (rc != FAPI_STATUS_SUCCESS) {
rc = -EIO;

9
drivers/fpga/fpga_altera_agilex_bridge.c
View File

@ -270,18 +270,21 @@ static int32_t fpga_reconfig_status_validate(struct fpga_config_status *reconfig
return MBOX_CONFIG_STATUS_STATE_CONFIG;
}
if (ret && ret != MBOX_CONFIG_STATUS_STATE_CONFIG)
if (ret && ret != MBOX_CONFIG_STATUS_STATE_CONFIG) {
return ret;
}
/* Make sure nStatus is not 0 */
ret = reconfig_status_resp->pin_status.pin_status;
if (!(ret & RECONFIG_PIN_STATUS_NSTATUS))
if (!(ret & RECONFIG_PIN_STATUS_NSTATUS)) {
return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
}
ret = reconfig_status_resp->soft_function_status;
if ((ret & RECONFIG_SOFTFUNC_STATUS_CONF_DONE) &&
(ret & RECONFIG_SOFTFUNC_STATUS_INIT_DONE) && !reconfig_status_resp->state)
(ret & RECONFIG_SOFTFUNC_STATUS_INIT_DONE) && !reconfig_status_resp->state) {
return 0; /* Configuration success */
}
return MBOX_CONFIG_STATUS_STATE_CONFIG;
}

3
drivers/fpga/fpga_eos_s3.c
View File

@ -36,8 +36,9 @@ static enum FPGA_status eos_s3_fpga_get_status(const struct device *dev)
if (PMU->FB_STATUS == FPGA_STATUS_ACTIVE) {
return FPGA_STATUS_ACTIVE;
} else
} else {
return FPGA_STATUS_INACTIVE;
}
}
static const char *eos_s3_fpga_get_info(const struct device *dev)

3
drivers/gpio/gpio_pca95xx.c
View File

@ -124,8 +124,9 @@ static int read_port_reg(const struct device *dev, uint8_t reg, uint8_t pin,
uint8_t b_buf;
int ret;
if (pin >= 8)
if (pin >= 8) {
reg++;
}
ret = i2c_reg_read_byte_dt(&config->bus, reg, &b_buf);
if (ret != 0) {

3
drivers/gpio/gpio_rt1718s.h
View File

@ -155,8 +155,9 @@ static inline int rt1718s_reg_burst_write(const struct device *dev, uint8_t star
static inline int rt1718s_reg_update(const struct device *dev, uint8_t reg_addr, uint8_t reg_val,
uint8_t new_val)
{
if (reg_val == new_val)
if (reg_val == new_val) {
return 0;
}
return rt1718s_reg_write_byte(dev, reg_addr, new_val);
}

6
drivers/hwspinlock/sqn_hwspinlock.c
View File

@ -56,12 +56,14 @@ static int sqn_hwspinlock_trylock(const struct device *dev, uint32_t id)
*/
cpuid = mpidr_to_cpuid(read_mpidr_el1());
if (sys_read8(get_lock_addr(dev, id)) == cpuid)
if (sys_read8(get_lock_addr(dev, id)) == cpuid) {
return 0;
}
sys_write8(cpuid, get_lock_addr(dev, id));
if (sys_read8(get_lock_addr(dev, id)) == cpuid)
if (sys_read8(get_lock_addr(dev, id)) == cpuid) {
return 0;
}
return -EBUSY;
}

6
drivers/i2c/i2c_ene_kb1200.c
View File

@ -145,8 +145,9 @@ static int i2c_kb1200_poll_write(const struct device *dev, struct i2c_msg msg, u
}
config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL;
while (data->state != STATE_COMPLETE)
while (data->state != STATE_COMPLETE) {
;
}
data->state = STATE_IDLE;
if (data->err_code != 0) {
/* reset HW */
@ -187,8 +188,9 @@ static int i2c_kb1200_poll_read(const struct device *dev, struct i2c_msg msg, ui
}
config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL;
while (data->state != STATE_COMPLETE)
while (data->state != STATE_COMPLETE) {
;
}
data->state = STATE_IDLE;
if (data->err_code != 0) {
/* reset HW */

3
drivers/i2c/i2c_npcx_controller.c
View File

@ -425,8 +425,9 @@ static int i2c_ctrl_wait_stop_completed(const struct device *dev, int timeout)
* Wait till i2c bus is idle. This bit is cleared to 0
* automatically after the STOP condition is generated.
*/
if (!IS_BIT_SET(inst->SMBCTL1, NPCX_SMBCTL1_STOP))
if (!IS_BIT_SET(inst->SMBCTL1, NPCX_SMBCTL1_STOP)) {
break;
}
k_msleep(1);
} while (--timeout);

6
drivers/i2s/i2s_mcux_sai.c
View File

@ -151,8 +151,9 @@ static void i2s_tx_stream_disable(const struct device *dev, bool drop)
dma_stop(dev_dma, strm->dma_channel);
/* wait for TX FIFO to drain before disabling */
while ((dev_cfg->base->TCSR & I2S_TCSR_FWF_MASK) == 0)
while ((dev_cfg->base->TCSR & I2S_TCSR_FWF_MASK) == 0) {
;
}
/* Disable the channel FIFO */
dev_cfg->base->TCR3 &= ~I2S_TCR3_TCE_MASK;
@ -196,8 +197,9 @@ static void i2s_rx_stream_disable(const struct device *dev,
SAI_RxEnable(dev_cfg->base, false);
/* wait for Receiver to disable */
while (dev_cfg->base->RCSR & I2S_RCSR_RE_MASK)
while (dev_cfg->base->RCSR & I2S_RCSR_RE_MASK) {
;
}
/* reset the FIFO pointer and clear error flags */
dev_cfg->base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK);
dev_cfg->base->RCSR &= ~I2S_RCSR_SR_MASK;

3
drivers/interrupt_controller/intc_ite_it8xxx2.c
View File

@ -282,8 +282,9 @@ void soc_interrupt_init(void)
#endif
/* Ensure interrupts of soc are disabled at default */
for (int i = 0; i < ARRAY_SIZE(reg_enable); i++)
for (int i = 0; i < ARRAY_SIZE(reg_enable); i++) {
*reg_enable[i] = 0;
}
/*
* WORKAROUND: In the it8xxx2 chip, the interrupt for INT0 is reserved.

3
drivers/interrupt_controller/intc_plic.c
View File

@ -295,8 +295,9 @@ void riscv_plic_set_priority(uint32_t irq, uint32_t priority)
const uint32_t local_irq = irq_from_level_2(irq);
mem_addr_t prio_addr = config->prio + (local_irq * sizeof(uint32_t));
if (priority > config->max_prio)
if (priority > config->max_prio) {
priority = config->max_prio;
}
sys_write32(priority, prio_addr);
}

3
drivers/interrupt_controller/intc_swerv_pic.c
View File

@ -229,8 +229,9 @@ int arch_irq_is_enabled(unsigned int irq)
{
uint32_t mie;
if (irq > RISCV_MAX_GENERIC_IRQ)
if (irq > RISCV_MAX_GENERIC_IRQ) {
return swerv_pic_irq_is_enabled(irq);
}
__asm__ volatile ("csrr %0, mie" : "=r" (mie));

8
drivers/ipm/ipm_esp32.c
View File

@ -68,9 +68,10 @@ IRAM_ATTR static void esp32_ipm_isr(const struct device *dev)
}
/* first of all take the own of the shared memory */
while (!atomic_cas(&dev_data->control->lock,
ESP32_IPM_LOCK_FREE_VAL, dev_data->this_core_id))
while (!atomic_cas(&dev_data->control->lock, ESP32_IPM_LOCK_FREE_VAL,
dev_data->this_core_id)) {
;
}
if (dev_data->cb) {
@ -235,8 +236,9 @@ static int esp32_ipm_init(const struct device *dev)
LOG_DBG("Waiting CPU0 to sync");
while (!atomic_cas(&data->control->lock,
ESP32_IPM_LOCK_FREE_VAL, data->this_core_id))
ESP32_IPM_LOCK_FREE_VAL, data->this_core_id)) {
;
}
atomic_set(&data->control->lock, ESP32_IPM_LOCK_FREE_VAL);

3
drivers/ipm/ipm_ivshmem.c
View File

@ -60,8 +60,9 @@ static void ivshmem_ipm_event_loop_thread(void *arg, void *p2, void *p3)
/* get ready for next signal */
k_poll_signal_reset(&sig);
if (dev_data->cb)
if (dev_data->cb) {
dev_data->cb(dev, dev_data->user_data, 0, NULL);
}
}
}

3
drivers/ipm/ipm_stm32_hsem.c
View File

@ -52,8 +52,9 @@ void stm32_hsem_mailbox_ipm_rx_isr(const struct device *dev)
uint32_t mask_semid = (1U << data->rx_semid);
/* Check semaphore rx_semid interrupt status */
if (!ll_hsem_isactiveflag_cmisr(HSEM, mask_semid))
if (!ll_hsem_isactiveflag_cmisr(HSEM, mask_semid)) {
return;
}
/* Notify user with NULL data pointer */
if (data->callback) {

3
drivers/mbox/mbox_stm32_hsem.c
View File

@ -115,8 +115,9 @@ static void mbox_dispatcher(const struct device *dev)
struct mbox_stm32_hsem_data *data = dev->data;
/* Check semaphore rx_semid interrupt status */
if (!stm32_hsem_is_rx_interrupt_active())
if (!stm32_hsem_is_rx_interrupt_active()) {
return;
}
if (data->cb != NULL) {
data->cb(dev, MBOX_RX_HSEM_ID, data->user_data, NULL);

10
drivers/memc/memc_mspi_aps6404l.c
View File

@ -144,13 +144,14 @@ static void acquire(const struct device *psram)
if (cfg->sw_multi_periph) {
while (mspi_dev_config(cfg->bus, &cfg->dev_id,
MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg))
MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg)) {
;
}
} else {
while (mspi_dev_config(cfg->bus, &cfg->dev_id,
MSPI_DEVICE_CONFIG_NONE, NULL))
MSPI_DEVICE_CONFIG_NONE, NULL)) {
;
}
}
}
@ -159,8 +160,9 @@ static void release(const struct device *psram)
const struct memc_mspi_aps6404l_config *cfg = psram->config;
struct memc_mspi_aps6404l_data *data = psram->data;
while (mspi_get_channel_status(cfg->bus, cfg->port))
while (mspi_get_channel_status(cfg->bus, cfg->port)) {
;
}
k_sem_give(&data->lock);
}

3
drivers/pinctrl/renesas/rcar/pfc_r8a779f0.c
View File

@ -595,8 +595,9 @@ const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index)
{
if (RCAR_IS_GP_PIN(pin) == false)
if (RCAR_IS_GP_PIN(pin) == false) {
return -EINVAL;
}
*reg_index = pin / 32;

6
drivers/ps2/ps2_npcx_controller.c
View File

@ -227,10 +227,12 @@ static int ps2_npcx_ctrl_is_rx_error(const struct device *dev)
status = inst->PSTAT & (BIT(NPCX_PSTAT_PERR) | BIT(NPCX_PSTAT_RFERR));
if (status) {
if (status & BIT(NPCX_PSTAT_PERR))
if (status & BIT(NPCX_PSTAT_PERR)) {
LOG_ERR("RX parity error");
if (status & BIT(NPCX_PSTAT_RFERR))
}
if (status & BIT(NPCX_PSTAT_RFERR)) {
LOG_ERR("RX Frame error");
}
return -EIO;
}

3
drivers/regulator/regulator_nxp_vref.c
View File

@ -43,8 +43,9 @@ static int regulator_nxp_vref_enable(const struct device *dev)
*csr |= VREF_CSR_HCBGEN_MASK;
/* Monitor until stable */
while (!(*csr & VREF_CSR_VREFST_MASK))
while (!(*csr & VREF_CSR_VREFST_MASK)) {
;
}
/* Enable output buffer */
*csr |= VREF_CSR_BUF21EN_MASK;

4
drivers/sdhc/sdhc_spi.c
View File

@ -184,9 +184,9 @@ static int sdhc_spi_card_busy(const struct device *dev)
if (response == 0xFF) {
return 0;
} else
} else {
return 1;
}
}
/* Waits for SPI SD card to stop sending busy signal */

3
drivers/sensor/adi/adxl367/adxl367.c
View File

@ -121,9 +121,10 @@ static int adxl367_set_op_mode(const struct device *dev,
return ret;
}
if (op_mode == ADXL367_MEASURE)
if (op_mode == ADXL367_MEASURE) {
/* Wait 100 ms to allow the acceleration outputs to settle */
k_sleep(K_MSEC(100));
}
return 0;
}

6
drivers/sensor/ti/lm95234/lm95234.c
View File

@ -147,14 +147,16 @@ static int lm95234_sample_fetch(const struct device *dev,
switch ((uint32_t)chan) {
case SENSOR_CHAN_ALL:
ret = lm95234_fetch_temp(cfg, data, SENSOR_CHAN_AMBIENT_TEMP, &data->local);
if (ret)
if (ret) {
return ret;
}
for (int i = 0; i < ARRAY_SIZE(data->remote); i++) {
ret = lm95234_fetch_temp(cfg, data,
SENSOR_CHAN_LM95234_REMOTE_TEMP_1 + i,
&data->remote[i]);
if (ret)
if (ret) {
return ret;
}
}
break;
case SENSOR_CHAN_AMBIENT_TEMP:

9
drivers/serial/uart_bcm2711.c
View File

@ -80,8 +80,9 @@ static bool bcm2711_mu_lowlevel_can_putc(mem_addr_t base)
static void bcm2711_mu_lowlevel_putc(mem_addr_t base, uint8_t ch)
{
/* Wait until there is data in the FIFO */
while (!bcm2711_mu_lowlevel_can_putc(base))
while (!bcm2711_mu_lowlevel_can_putc(base)) {
;
}
/* Send the character */
sys_write32(ch, base + BCM2711_MU_IO);
@ -93,8 +94,9 @@ static void bcm2711_mu_lowlevel_init(mem_addr_t base, bool skip_baudrate_config,
uint32_t divider;
/* Wait until there is data in the FIFO */
while (!bcm2711_mu_lowlevel_can_putc(base))
while (!bcm2711_mu_lowlevel_can_putc(base)) {
;
}
/* Disable port */
sys_write32(0x0, base + BCM2711_MU_CNTL);
@ -148,8 +150,9 @@ static int uart_bcm2711_poll_in(const struct device *dev, unsigned char *c)
{
struct bcm2711_uart_data *uart_data = dev->data;
while (!bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr))
while (!bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr)) {
;
}
return sys_read32(uart_data->uart_addr + BCM2711_MU_IO) & 0xFF;
}

5
drivers/serial/uart_ql_usbserialport_s3b.c
View File

@ -51,9 +51,10 @@ static bool usbserial_rx_fifo_empty(void)
*/
static void uart_usbserial_poll_out(const struct device *dev, unsigned char c)
{
/* Wait for room in Tx FIFO */
while (usbserial_tx_fifo_full())
/* Wait for room in Tx FIFO */
while (usbserial_tx_fifo_full()) {
;
}
usbserial_regs->wdata = c;
}

6
drivers/spi/spi_pl022.c
View File

@ -741,8 +741,9 @@ static void spi_pl022_xfer(const struct device *dev)
data->rx_count = 0;
/* Ensure writable */
while (!SSP_TX_FIFO_EMPTY(cfg->reg))
while (!SSP_TX_FIFO_EMPTY(cfg->reg)) {
;
}
/* Drain RX FIFO */
while (SSP_RX_FIFO_NOT_EMPTY(cfg->reg))
SSP_READ_REG(SSP_DR(cfg->reg));
@ -762,8 +763,9 @@ static void spi_pl022_xfer(const struct device *dev)
fifo_cnt++;
}
while (data->rx_count < chunk_len && fifo_cnt > 0) {
if (!SSP_RX_FIFO_NOT_EMPTY(cfg->reg))
if (!SSP_RX_FIFO_NOT_EMPTY(cfg->reg)) {
continue;
}
txrx = SSP_READ_REG(SSP_DR(cfg->reg));

10
drivers/timer/ite_it8xxx2_timer.c
View File

@ -340,15 +340,15 @@ static int timer_init(enum ext_timer_idx ext_timer,
if (raw == EXT_RAW_CNT) {
hw_cnt = ms;
} else {
if (clock_source_sel == EXT_PSR_32P768K)
if (clock_source_sel == EXT_PSR_32P768K) {
hw_cnt = MS_TO_COUNT(32768, ms);
else if (clock_source_sel == EXT_PSR_1P024K)
} else if (clock_source_sel == EXT_PSR_1P024K) {
hw_cnt = MS_TO_COUNT(1024, ms);
else if (clock_source_sel == EXT_PSR_32)
} else if (clock_source_sel == EXT_PSR_32) {
hw_cnt = MS_TO_COUNT(32, ms);
else if (clock_source_sel == EXT_PSR_EC_CLK)
} else if (clock_source_sel == EXT_PSR_EC_CLK) {
hw_cnt = MS_TO_COUNT(EC_FREQ, ms);
else {
} else {
LOG_ERR("Timer %d clock source error !", ext_timer);
return -1;
}

3
drivers/timer/stm32_lptim_timer.c
View File

@ -162,8 +162,9 @@ static void lptim_set_autoreload(uint32_t arr)
/* Update autoreload register */
autoreload_next = arr;
if (!autoreload_ready)
if (!autoreload_ready) {
return;
}
/* The ARR register ready, we could set it directly */
if ((arr > 0) && (arr != LL_LPTIM_GetAutoReload(LPTIM))) {

3
drivers/timer/ti_dmtimer.c
View File

@ -54,8 +54,9 @@ static void ti_dm_timer_write_masks(uint32_t data, uint32_t reg, uint32_t mask,
static void ti_dmtimer_isr(void *data)
{
/* If no pending event */
if (!TI_DM_TIMER_READ(IRQSTATUS))
if (!TI_DM_TIMER_READ(IRQSTATUS)) {
return;
}
k_spinlock_key_t key = k_spin_lock(&lock);

3
drivers/watchdog/wdt_dw.c
View File

@ -186,8 +186,9 @@ static int dw_wdt_init(const struct device *dev)
}
#endif
ret = dw_wdt_probe((uint32_t)reg_base, dev_config->reset_pulse_length);
if (ret)
if (ret) {
return ret;
}
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(interrupts)
if (dev_config->irq_config) {

3
drivers/xen/dom0/domctl.c
View File

@ -114,8 +114,9 @@ int xen_domctl_get_paging_mempool_size(int domid, uint64_t *size_mb)
};
rc = do_domctl(&domctl);
if (rc)
if (rc) {
return rc;
}
*size_mb = domctl.u.paging_mempool.size;

3
drivers/xen/events.c
View File

@ -132,9 +132,10 @@ int bind_event_channel(evtchn_port_t port, evtchn_cb_t cb, void *data)
__ASSERT(cb != NULL, "%s: NULL callback for evtchn #%u\n",
__func__, port);
if (event_channels[port].cb != empty_callback)
if (event_channels[port].cb != empty_callback) {
LOG_WRN("%s: re-bind callback for evtchn #%u\n",
__func__, port);
}
event_channels[port].priv = data;
event_channels[port].cb = cb;

12
include/zephyr/drivers/dai.h
View File

@ -477,8 +477,9 @@ static inline int dai_ts_config(const struct device *dev, struct dai_ts_cfg *cfg
{
const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api;
if (!api->ts_config)
if (!api->ts_config) {
return -EINVAL;
}
return api->ts_config(dev, cfg);
}
@ -496,8 +497,9 @@ static inline int dai_ts_start(const struct device *dev, struct dai_ts_cfg *cfg)
{
const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api;
if (!api->ts_start)
if (!api->ts_start) {
return -EINVAL;
}
return api->ts_start(dev, cfg);
}
@ -515,8 +517,9 @@ static inline int dai_ts_stop(const struct device *dev, struct dai_ts_cfg *cfg)
{
const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api;
if (!api->ts_stop)
if (!api->ts_stop) {
return -EINVAL;
}
return api->ts_stop(dev, cfg);
}
@ -536,8 +539,9 @@ static inline int dai_ts_get(const struct device *dev, struct dai_ts_cfg *cfg,
{
const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api;
if (!api->ts_get)
if (!api->ts_get) {
return -EINVAL;
}
return api->ts_get(dev, cfg, tsd);
}

12
include/zephyr/drivers/hwspinlock.h
View File

@ -78,8 +78,9 @@ static inline int z_impl_hwspinlock_trylock(const struct device *dev, uint32_t i
const struct hwspinlock_driver_api *api =
(const struct hwspinlock_driver_api *)dev->api;
if (api->trylock == NULL)
if (api->trylock == NULL) {
return -ENOSYS;
}
return api->trylock(dev, id);
}
@ -100,8 +101,9 @@ static inline void z_impl_hwspinlock_lock(const struct device *dev, uint32_t id)
const struct hwspinlock_driver_api *api =
(const struct hwspinlock_driver_api *)dev->api;
if (api->lock != NULL)
if (api->lock != NULL) {
api->lock(dev, id);
}
}
/**
@ -120,8 +122,9 @@ static inline void z_impl_hwspinlock_unlock(const struct device *dev, uint32_t i
const struct hwspinlock_driver_api *api =
(const struct hwspinlock_driver_api *)dev->api;
if (api->unlock != NULL)
if (api->unlock != NULL) {
api->unlock(dev, id);
}
}
/**
@ -142,8 +145,9 @@ static inline uint32_t z_impl_hwspinlock_get_max_id(const struct device *dev)
const struct hwspinlock_driver_api *api =
(const struct hwspinlock_driver_api *)dev->api;
if (api->get_max_id == NULL)
if (api->get_max_id == NULL) {
return 0;
}
return api->get_max_id(dev);
}