107 lines
2.8 KiB
ArmAsm
107 lines
2.8 KiB
ArmAsm
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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/* exports */
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GTEXT(__start)
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/* imports */
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GTEXT(__initialize)
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GTEXT(_isr_wrapper)
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SECTION_FUNC(vectors, __start)
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#if defined(CONFIG_RISCV_GP)
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/* Initialize global pointer */
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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#endif
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.option norvc;
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#if defined(CONFIG_RISCV_VECTORED_MODE)
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#if defined(CONFIG_RISCV_HAS_CLIC)
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/*
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* CLIC vectored mode
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*
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* CLIC vectored mode uses mtvec exclusively for exception handling and
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* mtvec.base must be aligned to 64 bytes (this is done using
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* CONFIG_ARCH_SW_ISR_TABLE_ALIGN)
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*/
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la t0, _isr_wrapper
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addi t0, t0, 0x03 /* Enable CLIC vectored mode by setting LSB */
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csrw mtvec, t0
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/*
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* CLIC vectored mode has a similar concept to CLINT vectored mode,
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* where an interrupt vector table is used for specific interrupts.
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* However, in CLIC vectored mode, the handler table contains the
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* address of the interrupt handler instead of an opcode containing a
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* jump instruction, this is done by leveraging
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* CONFIG_IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS.
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* When an interrupt occurs in CLIC vectored mode, the address of the
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* handler entry from the vector table is loaded and then jumped to in
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* hardware. This time mtvt is used as the base address for the
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* interrupt table.
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*/
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la t0, _irq_vector_table
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csrw 0x307, t0 /* mtvt */
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#else /* !CONFIG_RISCV_HAS_CLIC */
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/*
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* CLINT vectored mode
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*
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* Set mtvec (Machine Trap-Vector Base-Address Register)
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* to _irq_vector_table (interrupt vector table). Add 1 to base
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* address of _irq_vector_table to indicate that vectored mode
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* is used (LSB = 0x1). CPU will mask the LSB out of
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* the address so that base address of _irq_vector_table is used.
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*
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* NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
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* of _irq_vector_table breaks this code.
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*/
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la t0, _irq_vector_table /* Load address of interrupt vector table */
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addi t0, t0, 0x01 /* Enable vectored mode by setting LSB */
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csrw mtvec, t0
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#endif /* CONFIG_RISCV_HAS_CLIC */
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#else /* !CONFIG_RISCV_VECTORED_MODE */
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#if defined(CONFIG_RISCV_HAS_CLIC) && !defined(CONFIG_LEGACY_CLIC)
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la t0, _isr_wrapper
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addi t0, t0, 0x03 /* Set mode bits to 3, signifying CLIC. Everything else is reserved. */
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csrw mtvec, t0
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#else /* !CONFIG_RISCV_HAS_CLIC || CONFIG_LEGACY_CLIC */
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/*
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* CLINT direct mode
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*
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* Set mtvec (Machine Trap-Vector Base-Address Register)
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* to _isr_wrapper.
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*/
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la t0, _isr_wrapper
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csrw mtvec, t0
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#endif /* CONFIG_RISCV_HAS_CLIC&& !CONFIG_LEGACY_CLIC */
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#endif /* CONFIG_RISCV_VECTORED_MODE */
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#if CONFIG_INCLUDE_RESET_VECTOR
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/* Jump to __reset */
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tail __reset
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#else
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/* Jump to __initialize */
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tail __initialize
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#endif
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