zephyr/soc
Marcin Szymczyk ab79670fd6 soc: nordic: vpr: remove IRQ handling and enable RISCV_PRIVILEGED
IRQ handling functions are now in interrupt controller.
Enable necessary KConfigs to support CLIC properly.
A nice side effect of enabling RISCV_PRIVILIGED is that
`vector.S` is no longer necessary as common code handles
that.

Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-04-23 15:35:12 +02:00
..
altr
ambiq
andestech soc: andestech: Remove l2_cache.c 2024-04-22 09:19:27 -04:00
arm
aspeed
atmel
brcm
cdns
common soc: riscv-privileged: support SoCs without reset vector 2024-04-22 06:50:12 -07:00
cypress
efinix/sapphire
ene/kb1200
espressif soc: espressif: Fix the cache size set calls 2024-04-19 10:07:15 +02:00
gaisler
gd/gd32
infineon/xmc
intel soc: x86: add gpio acpi resource enumeration 2024-04-22 06:50:38 -07:00
ite/ec soc: it8xxx2: kconfig: define CONFIG for variant chip 2024-04-18 11:13:38 +02:00
litex/litex_vexriscv
lowrisc/opentitan
microchip soc: arm: microchip: mec172x: Add macro to get pin mux value 2024-04-05 23:47:32 +03:00
native/inf_clock
neorv32
nordic soc: nordic: vpr: remove IRQ handling and enable RISCV_PRIVILEGED 2024-04-23 15:35:12 +02:00
nuvoton driver: reset: npcx: add driver support for reset controller 2024-04-16 09:09:13 +02:00
nxp drivers: nxp_enet: Correct PTP clock dependencies 2024-04-18 11:18:31 +02:00
openisa/rv32m1
qemu
quicklogic/eos_s3
raspberrypi
renesas
renode/riscv_virtual
rockchip
sifive/sifive_freedom arch/riscv: remove the `Kconfig.core` file 2024-04-05 16:46:01 +03:00
silabs
snps
st/stm32 soc: st: stm32: adding option to enable prefetch buffer 2024-04-22 06:49:32 -07:00
starfive/jh71xx soc: starfive: jh71xx: select 64BIT for SOC_JH7110 2024-04-09 14:20:39 +02:00
telink/tlsr
ti
xen
xlnx
CMakeLists.txt
Kconfig
Kconfig.v1
Kconfig.v1.choice
Kconfig.v2