zephyr/soc/riscv/openisa_rv32m1
Gerard Marull-Paretas 68799d507d arch: riscv: make __soc_is_irq optional
It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-23 09:57:57 +01:00
..
CMakeLists.txt
Kconfig
Kconfig.defconfig
Kconfig.soc
linker.ld
pinctrl_soc.h
soc.c soc: riscv: openisa_rv32m1: add missing includes 2024-01-19 15:13:53 +00:00
soc.h arch: riscv: define local soc_interrupt_init prototypes 2024-01-15 09:58:03 +01:00
soc_context.h
soc_irq.S arch: riscv: make __soc_is_irq optional 2024-01-23 09:57:57 +01:00
soc_offsets.h soc: riscv: openisa_rv32m1: add missing includes 2024-01-19 15:13:53 +00:00
soc_ri5cy.h
soc_zero_riscy.h
vector.S
vector_table.ld
wdog.S