Gerard Marull-Paretas f0fe6b8833 soc: riscv: nrf54h: fix VPR core dependencies ... The actual RISC-V core needs to select RISCV, and specific SoC CPU depend on it. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>		2024-02-13 15:15:45 +01:00
..
andes_v5	linker: Generate snippets files for dtcm and itcm	2024-01-24 22:10:11 -06:00
common	arch: riscv: make __soc_is_irq optional	2024-01-23 09:57:57 +01:00
efinix_sapphire	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
espressif_esp32	arch: riscv: make __soc_is_irq optional	2024-01-23 09:57:57 +01:00
gd_gd32	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
intel_niosv	soc: riscv: remove empty soc.h files	2024-01-19 15:13:53 +00:00
ite_ec	soc/it8xxx2: add support for raising EC bus to 24MHz	2024-01-31 16:43:46 +00:00
litex_vexriscv	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
microchip_miv	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
neorv32	…
nordic_nrf	soc: riscv: nrf54h: fix VPR core dependencies	2024-02-13 15:15:45 +01:00
openisa_rv32m1	arch: riscv: make __soc_is_irq optional	2024-01-23 09:57:57 +01:00
opentitan	soc/riscv/opentitan: Kconfig.defconfig.series: Set NUM_IRQS to 256	2024-01-26 19:34:09 -06:00
renode_virt	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
sifive_freedom	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
starfive_jh71xx	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
telink_tlsr	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
virt	soc: riscv: make RISCV_HAS_(C|P)LIC promptless	2024-01-23 09:57:57 +01:00
CMakeLists.txt	…