181 lines
5.0 KiB
C
181 lines
5.0 KiB
C
/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <soc/rtc_cntl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <soc/gpio_reg.h>
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#include <soc/syscon_reg.h>
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#include <soc/system_reg.h>
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#include <soc/cache_memory.h>
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#include "hal/soc_ll.h"
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#include "hal/wdt_hal.h"
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#include "esp_cpu.h"
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#include "esp_timer.h"
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#include "esp_spi_flash.h"
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#include "esp_clk_internal.h"
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#include <soc/interrupt_reg.h>
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#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
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#include <zephyr/kernel_structs.h>
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#include <kernel_internal.h>
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#include <string.h>
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#include <zephyr/toolchain.h>
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#include <soc.h>
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#ifdef CONFIG_MCUBOOT
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#include "bootloader_init.h"
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#endif /* CONFIG_MCUBOOT */
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extern void esp_reset_reason_init(void);
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/*
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* This is written in C rather than assembly since, during the port bring up,
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* Zephyr is being booted by the Espressif bootloader. With it, the C stack
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* is already set up.
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*/
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void __attribute__((section(".iram1"))) __esp_platform_start(void)
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{
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#ifdef CONFIG_RISCV_GP
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/* Configure the global pointer register
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* (This should be the first thing startup does, as any other piece of code could be
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* relaxed by the linker to access something relative to __global_pointer$)
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*/
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__asm__ __volatile__(".option push\n"
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".option norelax\n"
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"la gp, __global_pointer$\n"
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".option pop");
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#endif /* CONFIG_RISCV_GP */
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__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
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"csrw mtvec, t0\n");
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z_bss_zero();
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/* Disable normal interrupts. */
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csr_read_clear(mstatus, MSTATUS_MIE);
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esp_reset_reason_init();
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#ifdef CONFIG_MCUBOOT
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/* MCUboot early initialisation.
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*/
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bootloader_init();
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#else
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/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
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* related issues in application. Hence disable that as we are about to start
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* Zephyr environment.
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*/
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wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_disable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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/* Configure the Cache MMU size for instruction and rodata in flash. */
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extern uint32_t esp_rom_cache_set_idrom_mmu_size(uint32_t irom_size,
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uint32_t drom_size);
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extern int _rodata_reserved_start;
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uint32_t rodata_reserved_start_align =
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(uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
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uint32_t cache_mmu_irom_size =
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((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
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sizeof(uint32_t);
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esp_rom_cache_set_idrom_mmu_size(cache_mmu_irom_size,
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CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
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/* Enable wireless phy subsystem clock,
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* This needs to be done before the kernel starts
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*/
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REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
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SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
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/* Configures the CPU clock, RTC slow and fast clocks, and performs
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* RTC slow clock calibration.
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*/
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esp_clk_init();
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esp_timer_early_init();
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#if CONFIG_SOC_FLASH_ESP32
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spi_flash_guard_set(&g_flash_guard_default_ops);
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#endif
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#endif /* CONFIG_MCUBOOT */
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/*Initialize the esp32c3 interrupt controller */
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esp_intr_initialize();
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/* Start Zephyr */
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z_cstart();
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CODE_UNREACHABLE;
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}
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/* Boot-time static default printk handler, possibly to be overridden later. */
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int IRAM_ATTR arch_printk_char_out(int c)
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{
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if (c == '\n') {
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esp_rom_uart_tx_one_char('\r');
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}
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esp_rom_uart_tx_one_char(c);
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return 0;
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}
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void IRAM_ATTR esp_restart_noos(void)
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{
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/* Disable interrupts */
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csr_read_clear(mstatus, MSTATUS_MIE);
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/* Flush any data left in UART FIFOs */
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esp_rom_uart_tx_wait_idle(0);
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esp_rom_uart_tx_wait_idle(1);
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/* 2nd stage bootloader reconfigures SPI flash signals. */
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/* Reset them to the defaults expected by ROM */
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WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
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WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
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/* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */
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SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
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SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST |
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SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_EMAC_RST |
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SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST |
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BLE_REG_REST_BIT | BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
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REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
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/* Reset uart0 core first, then reset apb side. */
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SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
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/* Reset timer/spi/uart */
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
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SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
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/* Reset dma */
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
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REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
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/* Reset core */
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soc_ll_reset_core(0);
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while (true) {
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;
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}
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}
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void sys_arch_reboot(int type)
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{
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esp_restart_noos();
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}
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