484 lines
11 KiB
Plaintext
484 lines
11 KiB
Plaintext
/*
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* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
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* Copyright (c) 2019 ST Microelectronics
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* Copyright (c) 2019 Centaur Analytics, Inc
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* Copyright (C) 2020 Framework Computer LLC <ktl@frame.work>
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* Copyright (c) 2021 G-Technologies Sdn. Bhd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv6-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/dma/stm32_dma.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
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#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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#include <zephyr/dt-bindings/reset/stm32g0_reset.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0+";
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reg = <0>;
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cpu-power-states = <&stop0 &stop1>;
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};
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power-states {
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stop0: state0 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <1>;
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min-residency-us = <20>;
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};
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stop1: state1 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <2>;
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min-residency-us = <100>;
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};
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "st,stm32g0-hsi-clock";
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hsi-div = <1>;
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <0>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32g0-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
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reg = <0x40022000 0x400>;
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interrupts = <3 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <8>;
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erase-block-size = <2048>;
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/* maximum erase time(ms) for a 2K sector */
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max-erase-time = <40>;
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};
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};
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rcc: rcc@40021000 {
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compatible = "st,stm32f0-rcc";
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#clock-cells = <2>;
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reg = <0x40021000 0x400>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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exti: interrupt-controller@40021800 {
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compatible = "st,stm32g0-exti", "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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reg = <0x40021800 0x400>;
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num-lines = <16>;
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interrupts = <5 0>, <6 0>, <7 0>;
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interrupt-names = "line0-1", "line2-3", "line4-15";
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line-ranges = <0 2>, <2 2>, <4 12>;
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};
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pinctrl: pin-controller@50000000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x2000>;
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gpioa: gpio@50000000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
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};
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gpiob: gpio@50000400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
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};
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gpioc: gpio@50000800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
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};
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gpiod: gpio@50000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
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};
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gpiof: gpio@50001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>;
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};
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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interrupts = <2 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
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prescaler = <32768>;
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status = "disabled";
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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interrupts = <0 2>;
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status = "disabled";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
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resets = <&rctl STM32_RESET(APB1H, 14U)>;
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interrupts = <27 0>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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resets = <&rctl STM32_RESET(APB1L, 17U)>;
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interrupts = <28 0>;
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status = "disabled";
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};
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lptim1: timers@40007c00 {
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compatible = "st,stm32-lptim";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007c00 0x400>;
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interrupts = <17 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
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resets = <&rctl STM32_RESET(APB1H, 11U)>;
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interrupts = <13 0>, <14 0>;
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interrupt-names = "brk_up_trg_com", "cc";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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resets = <&rctl STM32_RESET(APB1L, 1U)>;
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interrupts = <16 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers14: timers@40002000 {
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00008000>;
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resets = <&rctl STM32_RESET(APB1H, 15U)>;
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interrupts = <19 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
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resets = <&rctl STM32_RESET(APB1H, 17U)>;
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interrupts = <21 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
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resets = <&rctl STM32_RESET(APB1H, 18U)>;
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interrupts = <22 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <23 0>;
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interrupt-names = "combined";
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <24 0>;
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interrupt-names = "combined";
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status = "disabled";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
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interrupts = <25 0>;
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <26 0>;
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status = "disabled";
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};
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adc1: adc@40012400 {
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compatible = "st,stm32-adc";
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reg = <0x40012400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>;
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interrupts = <12 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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/* Errata ES0418: For sampling time set to 1.5 or 3.5
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* cycles, the sampling in a single ADC conversion or in
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* the first conversion of a sequence takes one extra
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* cycle.
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* So instead of 2 4, we set 3 5.
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*/
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sampling-times = <3 5 8 13 20 40 80 161>;
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num-sampling-time-common-channels = <2>;
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st,adc-sequencer = <NOT_FULLY_CONFIGURABLE>;
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};
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dma1: dma@40020000 {
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compatible = "st,stm32-dma-v2";
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#dma-cells = <3>;
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reg = <0x40020000 0x400>;
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interrupts = <9 0 10 0 10 0 11 0 11 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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dma-requests = <5>;
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dma-offset = <0>;
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status = "disabled";
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};
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/* DMAMUX clock is enabled as long as DMA1 or DMA2 is enabled */
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dmamux1: dmamux@40020800 {
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compatible = "st,stm32-dmamux";
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#dma-cells = <3>;
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reg = <0x40020800 0x800>;
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interrupts = <11 0>;
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dma-channels = <5>;
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dma-generators = <4>;
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dma-requests= <49>;
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status = "disabled";
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};
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};
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die_temp: dietemp {
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compatible = "st,stm32-temp-cal";
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ts-cal1-addr = <0x1FFF75A8>;
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ts-cal2-addr = <0x1FFF75CA>;
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ts-cal1-temp = <30>;
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ts-cal2-temp = <130>;
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ts-cal-vrefanalog = <3000>;
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io-channels = <&adc1 12>;
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status = "disabled";
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};
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vref: vref {
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compatible = "st,stm32-vref";
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vrefint-cal-addr = <0x1FFF75AA>;
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vrefint-cal-mv = <3000>;
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io-channels = <&adc1 13>;
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status = "disabled";
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};
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vbat: vbat {
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compatible = "st,stm32-vbat";
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ratio = <3>;
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io-channels = <&adc1 14>;
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status = "disabled";
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};
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smbus1: smbus1 {
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compatible = "st,stm32-smbus";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c = <&i2c1>;
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status = "disabled";
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};
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smbus2: smbus2 {
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compatible = "st,stm32-smbus";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c = <&i2c2>;
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status = "disabled";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};
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