Filip Kokosinski ecf308e8de dts/andes: adjust the sizes of PLIC nodes ... This commit adjusts the sizes of the two PLIC nodes AE350 defines: * `plic0` size is changed from `0x04000000` to `0x02000000` * `plic_sw` size is changed from `0x04000000` to `0x00400000` Without these change, `plic0` address space would overlap with `plic_sw`, and with other memory-mapped peripherals. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>		2024-10-31 14:17:02 -05:00
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andes	dts/andes: adjust the sizes of PLIC nodes	2024-10-31 14:17:02 -05:00
efinix	dts: riscv: Fix incorrect plic size	2024-07-02 22:21:17 -04:00
espressif	soc: dts: esp32c3: esp8685: Add files to indicate support	2024-10-29 16:04:02 -07:00
gd	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
ite	drivers: pinctrl: ITE: Add a property configure pin current strength	2024-06-06 00:41:35 -07:00
lowrisc	dts: opentitan: update plic interrupt count to match spec	2024-03-22 09:23:46 +00:00
microchip	dts: mbox: add PolarFire SoC mailbox interface	2024-02-01 04:33:16 -05:00
niosv	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
nordic	soc: nordic: Remove the nRF54L15 EngA	2024-10-21 01:46:39 +01:00
openisa	soc/openisa: enable the `C` extension	2024-07-03 15:06:14 -04:00
qemu	dts: set the `riscv,isa` property for virt-based targets	2024-05-15 09:30:23 +02:00
sensry	board: sensry: Add support for sy1xx	2024-09-16 20:19:31 +02:00
sifive	dts: sifive: Update SoC compats	2024-04-18 14:56:00 +02:00
starfive	dts: jh7110: fix memory definitions	2024-04-09 14:20:39 +02:00
telink	…
neorv32.dtsi	dts/riscv: add `riscv` compatible string where it's missing	2024-01-31 10:41:49 +01:00
renode_riscv32_virt.dtsi	dts: riscv: add a SoC dtsi for Renode RISC-V Virt SoC	2024-01-08 12:35:10 +01:00
riscv32-litex-vexriscv.dtsi	drivers: watchdog: litex: add litex watchdog	2024-08-19 10:02:01 -04:00