286 lines
6.5 KiB
ArmAsm
286 lines
6.5 KiB
ArmAsm
/*
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* Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* based on arch/riscv/core/isr.S and arch/nios2/core/exception.S
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/kernel_structs.h>
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#include <offsets_short.h>
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#include <zephyr/arch/cpu.h>
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#include <mips/regdef.h>
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#include <mips/mipsregs.h>
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#define ESF_O(FIELD) __z_arch_esf_t_##FIELD##_OFFSET
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#define THREAD_O(FIELD) _thread_offset_to_##FIELD
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/* Convenience macros for loading/storing register states. */
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#define DO_CALLEE_SAVED(op, reg) \
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op s0, THREAD_O(s0)(reg) ;\
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op s1, THREAD_O(s1)(reg) ;\
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op s2, THREAD_O(s2)(reg) ;\
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op s3, THREAD_O(s3)(reg) ;\
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op s4, THREAD_O(s4)(reg) ;\
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op s5, THREAD_O(s5)(reg) ;\
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op s6, THREAD_O(s6)(reg) ;\
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op s7, THREAD_O(s7)(reg) ;\
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op s8, THREAD_O(s8)(reg) ;
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#define STORE_CALLEE_SAVED(reg) \
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DO_CALLEE_SAVED(OP_STOREREG, reg)
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#define LOAD_CALLEE_SAVED(reg) \
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DO_CALLEE_SAVED(OP_LOADREG, reg)
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#define DO_CALLER_SAVED(op) \
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op ra, ESF_O(ra)(sp) ;\
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op gp, ESF_O(gp)(sp) ;\
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op AT, ESF_O(at)(sp) ;\
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op t0, ESF_O(t0)(sp) ;\
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op t1, ESF_O(t1)(sp) ;\
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op t2, ESF_O(t2)(sp) ;\
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op t3, ESF_O(t3)(sp) ;\
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op t4, ESF_O(t4)(sp) ;\
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op t5, ESF_O(t5)(sp) ;\
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op t6, ESF_O(t6)(sp) ;\
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op t7, ESF_O(t7)(sp) ;\
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op t8, ESF_O(t8)(sp) ;\
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op t9, ESF_O(t9)(sp) ;\
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op a0, ESF_O(a0)(sp) ;\
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op a1, ESF_O(a1)(sp) ;\
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op a2, ESF_O(a2)(sp) ;\
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op a3, ESF_O(a3)(sp) ;\
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op v0, ESF_O(v0)(sp) ;\
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op v1, ESF_O(v1)(sp) ;
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#define STORE_CALLER_SAVED() \
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addi sp, sp, -__z_arch_esf_t_SIZEOF ;\
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DO_CALLER_SAVED(OP_STOREREG) ;
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#define LOAD_CALLER_SAVED() \
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DO_CALLER_SAVED(OP_LOADREG) ;\
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addi sp, sp, __z_arch_esf_t_SIZEOF ;
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/* imports */
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GTEXT(_Fault)
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GTEXT(_k_neg_eagain)
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GTEXT(z_thread_mark_switched_in)
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/* exports */
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GTEXT(__isr_vec)
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SECTION_FUNC(exception.entry, __isr_vec)
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la k0, _mips_interrupt
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jr k0
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SECTION_FUNC(exception.other, _mips_interrupt)
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.set noat
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/*
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* Save caller-saved registers on current thread stack.
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*/
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STORE_CALLER_SAVED()
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/* save CP0 registers */
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mfhi t0
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mflo t1
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OP_STOREREG t0, ESF_O(hi)(sp)
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OP_STOREREG t1, ESF_O(lo)(sp)
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mfc0 t0, CP0_EPC
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OP_STOREREG t0, ESF_O(epc)(sp)
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mfc0 t1, CP0_BADVADDR
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OP_STOREREG t1, ESF_O(badvaddr)(sp)
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mfc0 t0, CP0_STATUS
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OP_STOREREG t0, ESF_O(status)(sp)
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mfc0 t1, CP0_CAUSE
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OP_STOREREG t1, ESF_O(cause)(sp)
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/*
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* Check if exception is the result of an interrupt or not.
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*/
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li k0, CAUSE_EXP_MASK
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and k1, k0, t1
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srl k1, k1, CAUSE_EXP_SHIFT
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/* ExcCode == 8 (SYSCALL) ? */
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li k0, 8
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beq k0, k1, is_kernel_syscall
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/* a0 = ((cause & status) & CAUSE_IP_MASK) >> CAUSE_IP_SHIFT */
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and t1, t1, t0
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li a0, CAUSE_IP_MASK
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and a0, a0, t1
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srl a0, a0, CAUSE_IP_SHIFT
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/* ExcCode == 0 (INTERRUPT) ? if not, go to unhandled */
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bnez k1, unhandled
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/* cause IP_MASK != 0 ? */
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bnez a0, is_interrupt
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unhandled:
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move a0, sp
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jal _Fault
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eret
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is_kernel_syscall:
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/*
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* A syscall is the result of an syscall instruction, in which case the
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* EPC will contain the address of the syscall instruction.
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* Increment saved EPC by 4 to prevent triggering the same syscall
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* again upon exiting the ISR.
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*/
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OP_LOADREG k0, ESF_O(epc)(sp)
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addi k0, k0, 4
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OP_STOREREG k0, ESF_O(epc)(sp)
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#ifdef CONFIG_IRQ_OFFLOAD
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/*
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* Determine if the system call is the result of an IRQ offloading.
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* Done by checking if _offload_routine is not pointing to NULL.
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* If NULL, jump to reschedule to perform a context-switch, otherwise,
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* jump to is_interrupt to handle the IRQ offload.
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*/
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la t0, _offload_routine
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OP_LOADREG t1, 0(t0)
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/*
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* Put 0 into a0: call z_mips_enter_irq() with ipending==0
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* to prevent spurious interrupt.
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*/
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move a0, zero
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bnez t1, is_interrupt
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#endif /* CONFIG_IRQ_OFFLOAD */
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/*
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* Go to reschedule to handle context-switch
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*/
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j reschedule
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is_interrupt:
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/*
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* Save current thread stack pointer and switch
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* stack pointer to interrupt stack.
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*/
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/* Save thread stack pointer to temp register k0 */
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move k0, sp
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/* Switch to interrupt stack */
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la k1, _kernel
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OP_LOADREG sp, _kernel_offset_to_irq_stack(k1)
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/*
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* Save thread stack pointer on interrupt stack
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*/
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addi sp, sp, -16
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OP_STOREREG k0, 0(sp)
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on_irq_stack:
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/*
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* Enter C interrupt handling code. Value of ipending will be the
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* function parameter since we put it in a0
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*/
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jal z_mips_enter_irq
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on_thread_stack:
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/* Restore thread stack pointer */
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OP_LOADREG sp, 0(sp)
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#ifdef CONFIG_PREEMPT_ENABLED
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/*
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* Check if we need to perform a reschedule
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*/
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/* Get pointer to _kernel.current */
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OP_LOADREG t2, _kernel_offset_to_current(k1)
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/*
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* Check if next thread to schedule is current thread.
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* If yes do not perform a reschedule
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*/
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OP_LOADREG t3, _kernel_offset_to_ready_q_cache(k1)
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beq t3, t2, no_reschedule
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#else
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j no_reschedule
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#endif /* CONFIG_PREEMPT_ENABLED */
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reschedule:
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/*
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* Check if the current thread is the same as the thread on the ready Q. If
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* so, do not reschedule.
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* Note:
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* Sometimes this code is execute back-to-back before the target thread
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* has a chance to run. If this happens, the current thread and the
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* target thread will be the same.
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*/
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la t0, _kernel
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OP_LOADREG t2, _kernel_offset_to_current(t0)
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OP_LOADREG t3, _kernel_offset_to_ready_q_cache(t0)
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beq t2, t3, no_reschedule
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/* Get reference to _kernel */
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la t0, _kernel
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/* Get pointer to _kernel.current */
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OP_LOADREG t1, _kernel_offset_to_current(t0)
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/*
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* Save callee-saved registers of current kernel thread
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* prior to handle context-switching
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*/
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STORE_CALLEE_SAVED(t1)
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skip_callee_saved_reg:
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/*
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* Save stack pointer of current thread and set the default return value
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* of z_swap to _k_neg_eagain for the thread.
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*/
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OP_STOREREG sp, _thread_offset_to_sp(t1)
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la t2, _k_neg_eagain
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lw t3, 0(t2)
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sw t3, _thread_offset_to_swap_return_value(t1)
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/* Get next thread to schedule. */
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OP_LOADREG t1, _kernel_offset_to_ready_q_cache(t0)
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/*
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* Set _kernel.current to new thread loaded in t1
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*/
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OP_STOREREG t1, _kernel_offset_to_current(t0)
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/* Switch to new thread stack */
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OP_LOADREG sp, _thread_offset_to_sp(t1)
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/* Restore callee-saved registers of new thread */
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LOAD_CALLEE_SAVED(t1)
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#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
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jal z_thread_mark_switched_in
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#endif
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/* fallthrough */
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no_reschedule:
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/* restore CP0 */
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OP_LOADREG t1, ESF_O(hi)(sp)
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OP_LOADREG t2, ESF_O(lo)(sp)
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mthi t1
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mtlo t2
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OP_LOADREG k0, ESF_O(epc)(sp)
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mtc0 k0, CP0_EPC
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OP_LOADREG k1, ESF_O(status)(sp)
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mtc0 k1, CP0_STATUS
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ehb
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/* Restore caller-saved registers from thread stack */
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LOAD_CALLER_SAVED()
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/* exit ISR */
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eret
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