Chad Karaginides f8b9faff24 arch: arm64: Added ISBs after SCTLR Modifications ... Per the ARMv8 architecture document, modification of the system control register is a context-changing operation. Context-changing operations are only guaranteed to be seen after a context synchronization event. An ISB is a context synchronization event. One has been placed after each SCTLR modification. Issue was found running full speed on target. Signed-off-by: Chad Karaginides <quic_chadk@quicinc.com>		2023-05-25 16:33:03 -04:00
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arc	ARC: MPU: Add MPUv8 fixes	2023-05-25 08:27:34 +00:00
arm	barriers: Move __ISB() to the new API	2023-05-24 13:13:57 -04:00
arm64	arch: arm64: Added ISBs after SCTLR Modifications	2023-05-25 16:33:03 -04:00
common	revert: "linker: rom_start_offset: add to address"	2023-03-30 18:19:32 -04:00
mips	…
nios2	arch: nios2: Remove unused absolute symbols	2023-04-18 10:51:28 -04:00
posix	arch posix: posix_cheats.h main() type changed in comment	2023-04-14 09:55:48 +02:00
riscv	arch: riscv: Enable builds without the multithreading	2023-05-25 16:15:54 +02:00
sparc	arch: sparc: Remove unused absolute symbols	2023-04-18 10:51:28 -04:00
x86	arch: x86: ia32: don't create FP context for NULL thread	2023-05-24 12:41:06 -04:00
xtensa	arch: xtensa: Enable builds without the multithreading	2023-05-25 16:15:54 +02:00
CMakeLists.txt	…
Kconfig	barriers: Enable builtin barriers for RISCV	2023-05-25 06:29:03 -04:00