407 lines
11 KiB
C
407 lines
11 KiB
C
/*
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* Copyright (c) 2017 ARM Ltd
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* Copyright (c) 2016 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file Driver for the Nordic Semiconductor nRF5X GPIO module.
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <gpio.h>
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#include <soc.h>
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#include <sys_io.h>
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#include "nrf5_common.h"
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#include "gpio_utils.h"
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#if defined(CONFIG_SOC_SERIES_NRF51X)
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#define GPIOTE_CHAN_COUNT (4)
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#elif defined(CONFIG_SOC_SERIES_NRF52X)
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#define GPIOTE_CHAN_COUNT (8)
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#else
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#error "Platform not defined."
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#endif
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/* GPIO structure for nRF5X. More detailed description of each register can be found in nrf5X.h */
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struct _gpio {
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__I u32_t RESERVED0[321];
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__IO u32_t OUT;
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__IO u32_t OUTSET;
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__IO u32_t OUTCLR;
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__I u32_t IN;
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__IO u32_t DIR;
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__IO u32_t DIRSET;
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__IO u32_t DIRCLR;
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__IO u32_t LATCH;
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__IO u32_t DETECTMODE;
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__I u32_t RESERVED1[118];
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__IO u32_t PIN_CNF[32];
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};
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/* GPIOTE structure for nRF5X. More detailed description of each register can be found in nrf5X.h */
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struct _gpiote {
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__O u32_t TASKS_OUT[8];
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__I u32_t RESERVED0[4];
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__O u32_t TASKS_SET[8];
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__I u32_t RESERVED1[4];
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__O u32_t TASKS_CLR[8];
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__I u32_t RESERVED2[32];
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__IO u32_t EVENTS_IN[8];
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__I u32_t RESERVED3[23];
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__IO u32_t EVENTS_PORT;
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__I u32_t RESERVED4[97];
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__IO u32_t INTENSET;
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__IO u32_t INTENCLR;
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__I u32_t RESERVED5[129];
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__IO u32_t CONFIG[8];
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};
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/** Configuration data */
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struct gpio_nrf5_config {
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/* GPIO module base address */
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u32_t gpio_base_addr;
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/* Port Control module base address */
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u32_t port_base_addr;
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/* GPIO Task Event base address */
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u32_t gpiote_base_addr;
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};
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struct gpio_nrf5_data {
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/* list of registered callbacks */
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sys_slist_t callbacks;
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/* pin callback routine enable flags, by pin number */
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u32_t pin_callback_enables;
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/*@todo: move GPIOTE channel management to a separate module */
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u32_t gpiote_chan_mask;
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};
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/* convenience defines for GPIO */
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#define DEV_GPIO_CFG(dev) \
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((const struct gpio_nrf5_config * const)(dev)->config->config_info)
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#define DEV_GPIO_DATA(dev) \
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((struct gpio_nrf5_data * const)(dev)->driver_data)
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#define GPIO_STRUCT(dev) \
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((volatile struct _gpio *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
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/* convenience defines for GPIOTE */
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#define GPIOTE_STRUCT(dev) \
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((volatile struct _gpiote *)(DEV_GPIO_CFG(dev))->gpiote_base_addr)
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#define GPIO_SENSE_DISABLE (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
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#define GPIO_SENSE_ENABLE (GPIO_PIN_CNF_SENSE_Enabled << GPIO_PIN_CNF_SENSE_Pos)
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#define GPIO_PULL_DISABLE (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
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#define GPIO_PULL_DOWN (GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos)
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#define GPIO_PULL_UP (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos)
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#define GPIO_INPUT_CONNECT (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
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#define GPIO_INPUT_DISCONNECT (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
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#define GPIO_DIR_INPUT (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos)
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#define GPIO_DIR_OUTPUT (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos)
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#define GPIO_DRIVE_S0S1 (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_H0S1 (GPIO_PIN_CNF_DRIVE_H0S1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_S0H1 (GPIO_PIN_CNF_DRIVE_S0H1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_H0H1 (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_D0S1 (GPIO_PIN_CNF_DRIVE_D0S1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_D0H1 (GPIO_PIN_CNF_DRIVE_D0H1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_S0D1 (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIO_DRIVE_H0D1 (GPIO_PIN_CNF_DRIVE_H0D1 << GPIO_PIN_CNF_DRIVE_Pos)
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#define GPIOTE_CFG_EVT (GPIOTE_CONFIG_MODE_Event << GPIOTE_CONFIG_MODE_Pos)
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#define GPIOTE_CFG_TASK (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos)
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#define GPIOTE_CFG_POL_L2H (GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos)
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#define GPIOTE_CFG_POL_H2L (GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos)
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#define GPIOTE_CFG_POL_TOGG (GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos)
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#define GPIOTE_CFG_PIN(pin) ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk)
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#define GPIOTE_CFG_PIN_GET(config) ((config & GPIOTE_CONFIG_PSEL_Msk) >> \
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GPIOTE_CONFIG_PSEL_Pos)
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static int gpiote_find_channel(struct device *dev, u32_t pin)
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{
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volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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int i;
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for (i = 0; i < GPIOTE_CHAN_COUNT; i++) {
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if ((data->gpiote_chan_mask & BIT(i)) &&
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(GPIOTE_CFG_PIN_GET(gpiote->CONFIG[i]) == pin)) {
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return i;
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}
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}
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return -ENODEV;
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}
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/**
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* @brief Configure pin or port
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*/
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static int gpio_nrf5_config(struct device *dev,
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int access_op, u32_t pin, int flags)
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{
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/* Note D0D1 is not supported so we switch to S0S1. */
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static const u32_t drive_strength[4][4] = {
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{GPIO_DRIVE_S0S1, GPIO_DRIVE_S0H1, 0, GPIO_DRIVE_S0D1},
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{GPIO_DRIVE_H0S1, GPIO_DRIVE_H0H1, 0, GPIO_DRIVE_H0D1},
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{0, 0, 0, 0},
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{GPIO_DRIVE_D0S1, GPIO_DRIVE_D0H1, 0, GPIO_DRIVE_S0S1}
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};
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volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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volatile struct _gpio *gpio = GPIO_STRUCT(dev);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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/* Check pull */
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u8_t pull = GPIO_PULL_DISABLE;
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int ds_low = (flags & GPIO_DS_LOW_MASK) >> GPIO_DS_LOW_POS;
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int ds_high = (flags & GPIO_DS_HIGH_MASK) >> GPIO_DS_HIGH_POS;
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__ASSERT_NO_MSG(ds_low != 2);
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__ASSERT_NO_MSG(ds_high != 2);
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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pull = GPIO_PULL_UP;
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} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
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pull = GPIO_PULL_DOWN;
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}
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
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/* Set initial output value */
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if (pull == GPIO_PULL_UP) {
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gpio->OUTSET = BIT(pin);
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} else if (pull == GPIO_PULL_DOWN) {
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gpio->OUTCLR = BIT(pin);
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}
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/* Config as output */
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gpio->PIN_CNF[pin] = (GPIO_SENSE_DISABLE |
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drive_strength[ds_low][ds_high] |
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pull |
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GPIO_INPUT_DISCONNECT |
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GPIO_DIR_OUTPUT);
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} else {
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/* Config as input */
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gpio->PIN_CNF[pin] = (GPIO_SENSE_DISABLE |
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drive_strength[ds_low][ds_high] |
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pull |
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GPIO_INPUT_CONNECT |
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GPIO_DIR_INPUT);
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}
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} else {
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return -ENOTSUP;
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}
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if (flags & GPIO_INT) {
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u32_t config = 0;
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if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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config |= GPIOTE_CFG_POL_TOGG;
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} else if (flags & GPIO_INT_ACTIVE_HIGH) {
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config |= GPIOTE_CFG_POL_L2H;
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} else {
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config |= GPIOTE_CFG_POL_H2L;
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}
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} else { /* GPIO_INT_LEVEL */
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/*@todo: use SENSE for this? */
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return -ENOTSUP;
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}
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if (__builtin_popcount(data->gpiote_chan_mask) ==
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GPIOTE_CHAN_COUNT) {
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return -EIO;
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}
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/* check if already allocated to replace */
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int i = gpiote_find_channel(dev, pin);
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if (i < 0) {
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/* allocate a GPIOTE channel */
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i = __builtin_ffs(~(data->gpiote_chan_mask)) - 1;
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}
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data->gpiote_chan_mask |= BIT(i);
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/* configure GPIOTE channel */
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config |= GPIOTE_CFG_EVT;
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config |= GPIOTE_CFG_PIN(pin);
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gpiote->CONFIG[i] = config;
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}
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return 0;
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}
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static int gpio_nrf5_read(struct device *dev,
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int access_op, u32_t pin, u32_t *value)
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{
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volatile struct _gpio *gpio = GPIO_STRUCT(dev);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = (gpio->IN >> pin) & 0x1;
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} else {
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*value = gpio->IN;
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}
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return 0;
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}
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static int gpio_nrf5_write(struct device *dev,
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int access_op, u32_t pin, u32_t value)
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{
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volatile struct _gpio *gpio = GPIO_STRUCT(dev);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) { /* 1 */
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gpio->OUTSET = BIT(pin);
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} else { /* 0 */
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gpio->OUTCLR = BIT(pin);
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}
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} else {
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gpio->OUT = value;
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}
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return 0;
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}
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static int gpio_nrf5_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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_gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static int gpio_nrf5_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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int i;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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i = gpiote_find_channel(dev, pin);
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if (i < 0) {
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return i;
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}
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data->pin_callback_enables |= BIT(pin);
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/* clear event before any interrupt triggers */
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gpiote->EVENTS_IN[i] = 0;
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/* enable interrupt for the GPIOTE channel */
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gpiote->INTENSET = BIT(i);
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_nrf5_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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int i;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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i = gpiote_find_channel(dev, pin);
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if (i < 0) {
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return i;
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}
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data->pin_callback_enables &= ~(BIT(pin));
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/* disable interrupt for the GPIOTE channel */
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gpiote->INTENCLR = BIT(i);
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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/**
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* @brief Handler for port interrupts
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* @param dev Pointer to device structure for driver instance
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*
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* @return N/A
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*/
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static void gpio_nrf5_port_isr(void *arg)
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{
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struct device *dev = arg;
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volatile struct _gpiote *gpiote = GPIOTE_STRUCT(dev);
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struct gpio_nrf5_data *data = DEV_GPIO_DATA(dev);
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u32_t enabled_int, int_status = 0;
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int i;
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for (i = 0; i < GPIOTE_CHAN_COUNT; i++) {
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if (gpiote->EVENTS_IN[i]) {
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gpiote->EVENTS_IN[i] = 0;
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int_status |= BIT(GPIOTE_CFG_PIN_GET(gpiote->CONFIG[i]));
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}
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}
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enabled_int = int_status & data->pin_callback_enables;
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irq_disable(NRF5_IRQ_GPIOTE_IRQn);
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/* Call the registered callbacks */
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_gpio_fire_callbacks(&data->callbacks, (struct device *)dev,
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enabled_int);
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irq_enable(NRF5_IRQ_GPIOTE_IRQn);
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}
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static const struct gpio_driver_api gpio_nrf5_drv_api_funcs = {
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.config = gpio_nrf5_config,
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.read = gpio_nrf5_read,
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.write = gpio_nrf5_write,
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.manage_callback = gpio_nrf5_manage_callback,
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.enable_callback = gpio_nrf5_enable_callback,
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.disable_callback = gpio_nrf5_disable_callback,
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};
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/* Initialization for GPIO Port 0 */
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#ifdef CONFIG_GPIO_NRF5_P0
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static int gpio_nrf5_P0_init(struct device *dev);
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static const struct gpio_nrf5_config gpio_nrf5_P0_cfg = {
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.gpio_base_addr = NRF_GPIO_BASE,
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.port_base_addr = NRF_GPIO_BASE,
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.gpiote_base_addr = NRF_GPIOTE_BASE,
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};
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static struct gpio_nrf5_data gpio_data_P0;
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DEVICE_AND_API_INIT(gpio_nrf5_P0, CONFIG_GPIO_NRF5_P0_DEV_NAME, gpio_nrf5_P0_init,
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&gpio_data_P0, &gpio_nrf5_P0_cfg,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_nrf5_drv_api_funcs);
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static int gpio_nrf5_P0_init(struct device *dev)
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{
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IRQ_CONNECT(NRF5_IRQ_GPIOTE_IRQn, CONFIG_GPIO_NRF5_PORT_P0_PRI,
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gpio_nrf5_port_isr, DEVICE_GET(gpio_nrf5_P0), 0);
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irq_enable(NRF5_IRQ_GPIOTE_IRQn);
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return 0;
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}
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#endif /* CONFIG_GPIO_NRF5_P0 */
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