515 lines
12 KiB
C
515 lines
12 KiB
C
/*
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* Copyright (c) 2017, I-SENSE group of ICCS
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* Copyright (c) 2017 Linaro Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* I2C Driver for: STM32F1, STM32F2, STM32F4 and STM32L1
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*
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*/
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#include <clock_control/stm32_clock_control.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <kernel.h>
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#include <board.h>
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#include <errno.h>
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#include <i2c.h>
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#include "i2c_ll_stm32.h"
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(i2c_ll_stm32_v1);
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#define I2C_REQUEST_WRITE 0x00
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#define I2C_REQUEST_READ 0x01
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#define HEADER 0xF0
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#ifdef CONFIG_I2C_STM32_INTERRUPT
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static inline void handle_sb(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
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{
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u16_t saddr = data->slave_address;
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u8_t slave;
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if (I2C_ADDR_10_BITS & data->dev_config) {
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slave = (((saddr & 0x0300) >> 7) & 0xFF);
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u8_t header = slave | HEADER;
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if (data->current.is_restart == 0) {
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data->current.is_restart = 1;
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} else {
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header |= I2C_REQUEST_READ;
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data->current.is_restart = 0;
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}
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LL_I2C_TransmitData8(i2c, header);
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return;
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}
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slave = (saddr << 1) & 0xFF;
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if (data->current.is_write) {
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LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
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} else {
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LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
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}
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}
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static inline void handle_addr(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
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{
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if (I2C_ADDR_10_BITS & data->dev_config) {
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if (!data->current.is_write && data->current.is_restart) {
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data->current.is_restart = 0;
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LL_I2C_ClearFlag_ADDR(i2c);
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LL_I2C_GenerateStartCondition(i2c);
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return;
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}
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}
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if (!data->current.is_write) {
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if (data->current.len == 1) {
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/* Single byte reception: enable NACK and clear POS */
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
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} else if (data->current.len == 2) {
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/* 2-byte reception: enable NACK and set POS */
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
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LL_I2C_EnableBitPOS(i2c);
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}
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}
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LL_I2C_ClearFlag_ADDR(i2c);
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}
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static inline void handle_txe(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
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{
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if (data->current.len) {
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data->current.len--;
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if (data->current.len == 0) {
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/*
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* This is the last byte to transmit disable Buffer
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* interrupt and wait for a BTF interrupt
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*/
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LL_I2C_DisableIT_BUF(i2c);
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}
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LL_I2C_TransmitData8(i2c, *data->current.buf);
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data->current.buf++;
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} else {
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if (data->current.flags & I2C_MSG_STOP) {
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LL_I2C_GenerateStopCondition(i2c);
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}
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if (LL_I2C_IsActiveFlag_BTF(i2c)) {
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/* Read DR to clear BTF flag */
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LL_I2C_ReceiveData8(i2c);
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}
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k_sem_give(&data->device_sync_sem);
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}
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}
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static inline void handle_rxne(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
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{
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if (data->current.len > 0) {
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switch (data->current.len) {
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case 1:
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/* Single byte reception */
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if (data->current.flags & I2C_MSG_STOP) {
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LL_I2C_GenerateStopCondition(i2c);
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}
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LL_I2C_DisableIT_BUF(i2c);
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data->current.len--;
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*data->current.buf = LL_I2C_ReceiveData8(i2c);
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data->current.buf++;
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k_sem_give(&data->device_sync_sem);
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break;
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case 2:
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case 3:
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/*
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* 2-byte, 3-byte reception and for N-2, N-1,
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* N when N > 3
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*/
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LL_I2C_DisableIT_BUF(i2c);
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break;
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default:
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/* N byte reception when N > 3 */
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data->current.len--;
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*data->current.buf = LL_I2C_ReceiveData8(i2c);
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data->current.buf++;
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}
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}
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}
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static inline void handle_btf(I2C_TypeDef *i2c, struct i2c_stm32_data *data)
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{
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if (data->current.is_write) {
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handle_txe(i2c, data);
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} else {
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u32_t counter = 0;
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switch (data->current.len) {
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case 2:
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/*
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* Stop condition must be generated before reading the
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* last two bytes.
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*/
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if (data->current.flags & I2C_MSG_STOP) {
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LL_I2C_GenerateStopCondition(i2c);
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}
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for (counter = 2; counter > 0; counter--) {
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data->current.len--;
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*data->current.buf = LL_I2C_ReceiveData8(i2c);
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data->current.buf++;
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}
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k_sem_give(&data->device_sync_sem);
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break;
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case 3:
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/* Set NACK before reading N-2 byte*/
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
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data->current.len--;
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*data->current.buf = LL_I2C_ReceiveData8(i2c);
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data->current.buf++;
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break;
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default:
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handle_rxne(i2c, data);
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}
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}
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}
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void stm32_i2c_event_isr(void *arg)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG((struct device *)arg);
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struct i2c_stm32_data *data = DEV_DATA((struct device *)arg);
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I2C_TypeDef *i2c = cfg->i2c;
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if (LL_I2C_IsActiveFlag_SB(i2c)) {
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handle_sb(i2c, data);
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} else if (LL_I2C_IsActiveFlag_ADD10(i2c)) {
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LL_I2C_TransmitData8(i2c, data->slave_address);
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} else if (LL_I2C_IsActiveFlag_ADDR(i2c)) {
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handle_addr(i2c, data);
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} else if (LL_I2C_IsActiveFlag_BTF(i2c)) {
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handle_btf(i2c, data);
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} else if (LL_I2C_IsActiveFlag_TXE(i2c) && data->current.is_write) {
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handle_txe(i2c, data);
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} else if (LL_I2C_IsActiveFlag_RXNE(i2c) && !data->current.is_write) {
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handle_rxne(i2c, data);
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}
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}
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void stm32_i2c_error_isr(void *arg)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG((struct device *)arg);
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struct i2c_stm32_data *data = DEV_DATA((struct device *)arg);
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I2C_TypeDef *i2c = cfg->i2c;
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if (LL_I2C_IsActiveFlag_AF(i2c)) {
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LL_I2C_ClearFlag_AF(i2c);
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LL_I2C_GenerateStopCondition(i2c);
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data->current.is_nack = 1;
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k_sem_give(&data->device_sync_sem);
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return;
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}
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data->current.is_err = 1;
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k_sem_give(&data->device_sync_sem);
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}
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s32_t stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, u16_t saddr)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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s32_t ret = 0;
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ARG_UNUSED(next_msg_flags);
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data->current.len = msg->len;
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data->current.buf = msg->buf;
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data->current.flags = msg->flags;
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data->current.is_restart = 0;
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data->current.is_write = 1;
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data->current.is_nack = 0;
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data->current.is_err = 0;
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data->slave_address = saddr;
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LL_I2C_EnableIT_EVT(i2c);
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LL_I2C_EnableIT_ERR(i2c);
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
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if (msg->flags & I2C_MSG_RESTART) {
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LL_I2C_GenerateStartCondition(i2c);
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}
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LL_I2C_EnableIT_BUF(i2c);
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k_sem_take(&data->device_sync_sem, K_FOREVER);
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LL_I2C_DisableIT_BUF(i2c);
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if (data->current.is_nack || data->current.is_err) {
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if (data->current.is_nack)
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LOG_DBG("%s: NACK", __func__);
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if (data->current.is_err)
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LOG_DBG("%s: ERR %d", __func__,
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data->current.is_err);
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data->current.is_nack = 0;
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data->current.is_err = 0;
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ret = -EIO;
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}
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LL_I2C_DisableIT_EVT(i2c);
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LL_I2C_DisableIT_ERR(i2c);
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return ret;
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}
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s32_t stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, u16_t saddr)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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s32_t ret = 0;
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ARG_UNUSED(next_msg_flags);
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data->current.len = msg->len;
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data->current.buf = msg->buf;
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data->current.flags = msg->flags;
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data->current.is_restart = 0;
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data->current.is_write = 0;
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data->current.is_err = 0;
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data->slave_address = saddr;
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LL_I2C_EnableIT_EVT(i2c);
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LL_I2C_EnableIT_ERR(i2c);
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
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LL_I2C_GenerateStartCondition(i2c);
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LL_I2C_EnableIT_BUF(i2c);
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k_sem_take(&data->device_sync_sem, K_FOREVER);
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LL_I2C_DisableIT_BUF(i2c);
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if (data->current.is_err) {
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LOG_DBG("%s: ERR %d", __func__, data->current.is_err);
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data->current.is_err = 0;
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ret = -EIO;
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}
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LL_I2C_DisableIT_EVT(i2c);
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LL_I2C_DisableIT_ERR(i2c);
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return ret;
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}
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#else
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s32_t stm32_i2c_msg_write(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, u16_t saddr)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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u32_t len = msg->len;
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u8_t *buf = msg->buf;
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ARG_UNUSED(next_msg_flags);
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
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if (msg->flags & I2C_MSG_RESTART) {
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LL_I2C_GenerateStartCondition(i2c);
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while (!LL_I2C_IsActiveFlag_SB(i2c)) {
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;
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}
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if (I2C_ADDR_10_BITS & data->dev_config) {
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u8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
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u8_t header = slave | HEADER;
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LL_I2C_TransmitData8(i2c, header);
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while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
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;
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}
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slave = data->slave_address & 0xFF;
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LL_I2C_TransmitData8(i2c, slave);
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} else {
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u8_t slave = (saddr << 1) & 0xFF;
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LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_WRITE);
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}
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while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
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if (LL_I2C_IsActiveFlag_AF(i2c)) {
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LL_I2C_ClearFlag_AF(i2c);
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LL_I2C_GenerateStopCondition(i2c);
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LOG_DBG("%s: NACK", __func__);
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return -EIO;
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}
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}
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LL_I2C_ClearFlag_ADDR(i2c);
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}
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while (len) {
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while (1) {
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if (LL_I2C_IsActiveFlag_TXE(i2c)) {
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break;
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}
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if (LL_I2C_IsActiveFlag_AF(i2c)) {
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LL_I2C_ClearFlag_AF(i2c);
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LL_I2C_GenerateStopCondition(i2c);
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LOG_DBG("%s: NACK", __func__);
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return -EIO;
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}
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};
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LL_I2C_TransmitData8(i2c, *buf);
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buf++;
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len--;
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}
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while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
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;
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}
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if (msg->flags & I2C_MSG_STOP) {
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LL_I2C_GenerateStopCondition(i2c);
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}
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return 0;
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}
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s32_t stm32_i2c_msg_read(struct device *dev, struct i2c_msg *msg,
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u8_t *next_msg_flags, u16_t saddr)
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{
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const struct i2c_stm32_config *cfg = DEV_CFG(dev);
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struct i2c_stm32_data *data = DEV_DATA(dev);
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I2C_TypeDef *i2c = cfg->i2c;
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u32_t len = msg->len;
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u8_t *buf = msg->buf;
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ARG_UNUSED(next_msg_flags);
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_ACK);
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if (msg->flags & I2C_MSG_RESTART) {
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LL_I2C_GenerateStartCondition(i2c);
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while (!LL_I2C_IsActiveFlag_SB(i2c)) {
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;
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}
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if (I2C_ADDR_10_BITS & data->dev_config) {
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u8_t slave = (((saddr & 0x0300) >> 7) & 0xFF);
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u8_t header = slave | HEADER;
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LL_I2C_TransmitData8(i2c, header);
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while (!LL_I2C_IsActiveFlag_ADD10(i2c)) {
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;
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}
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slave = saddr & 0xFF;
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LL_I2C_TransmitData8(i2c, slave);
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while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
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;
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}
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LL_I2C_ClearFlag_ADDR(i2c);
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LL_I2C_GenerateStartCondition(i2c);
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while (!LL_I2C_IsActiveFlag_SB(i2c)) {
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;
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}
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header |= I2C_REQUEST_READ;
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LL_I2C_TransmitData8(i2c, header);
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} else {
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u8_t slave = ((saddr) << 1) & 0xFF;
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LL_I2C_TransmitData8(i2c, slave | I2C_REQUEST_READ);
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}
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while (!LL_I2C_IsActiveFlag_ADDR(i2c)) {
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if (LL_I2C_IsActiveFlag_AF(i2c)) {
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LL_I2C_ClearFlag_AF(i2c);
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LL_I2C_GenerateStopCondition(i2c);
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LOG_DBG("%s: NACK", __func__);
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return -EIO;
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}
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}
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if (len == 1) {
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/* Single byte reception: enable NACK and set STOP */
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
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} else if (len == 2) {
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/* 2-byte reception: enable NACK and set POS */
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
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LL_I2C_EnableBitPOS(i2c);
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}
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LL_I2C_ClearFlag_ADDR(i2c);
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}
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while (len) {
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while (!LL_I2C_IsActiveFlag_RXNE(i2c)) {
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;
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}
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switch (len) {
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case 1:
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if (msg->flags & I2C_MSG_STOP) {
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LL_I2C_GenerateStopCondition(i2c);
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}
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len--;
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*buf = LL_I2C_ReceiveData8(i2c);
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buf++;
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break;
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case 2:
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while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
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;
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}
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/*
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* Stop condition must be generated before reading the
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* last two bytes.
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*/
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if (msg->flags & I2C_MSG_STOP) {
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LL_I2C_GenerateStopCondition(i2c);
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}
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for (u32_t counter = 2; counter > 0; counter--) {
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len--;
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*buf = LL_I2C_ReceiveData8(i2c);
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buf++;
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}
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break;
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case 3:
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while (!LL_I2C_IsActiveFlag_BTF(i2c)) {
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;
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}
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/* Set NACK before reading N-2 byte*/
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LL_I2C_AcknowledgeNextData(i2c, LL_I2C_NACK);
|
|
/* Fall through */
|
|
default:
|
|
len--;
|
|
*buf = LL_I2C_ReceiveData8(i2c);
|
|
buf++;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
s32_t stm32_i2c_configure_timing(struct device *dev, u32_t clock)
|
|
{
|
|
const struct i2c_stm32_config *cfg = DEV_CFG(dev);
|
|
struct i2c_stm32_data *data = DEV_DATA(dev);
|
|
I2C_TypeDef *i2c = cfg->i2c;
|
|
|
|
switch (I2C_SPEED_GET(data->dev_config)) {
|
|
case I2C_SPEED_STANDARD:
|
|
LL_I2C_ConfigSpeed(i2c, clock, 100000, LL_I2C_DUTYCYCLE_2);
|
|
break;
|
|
case I2C_SPEED_FAST:
|
|
LL_I2C_ConfigSpeed(i2c, clock, 400000, LL_I2C_DUTYCYCLE_2);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|