101 lines
2.0 KiB
Plaintext
101 lines
2.0 KiB
Plaintext
/*
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* Copyright (c) 2023 Efinix Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "efinix,sapphire";
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compatible = "efinix,sapphire";
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chosen {
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zephyr,sram = &ram0;
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};
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ram0: memory@F9000000 {
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device_type = "memory";
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reg = <0xF9000000 DT_SIZE_K(192)>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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clock-frequency = <100000000>;
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compatible = "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv32ima_zicsr_zifencei";
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status = "okay";
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timebase-frequency = <100000000>;
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hlic: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "efinix,sapphire";
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ranges;
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plic0: interrupt-controller@f8c00000 {
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compatible = "sifive,plic-1.0.0";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts-extended = <&hlic 11>;
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reg = <0xf8c00000 0x04000000>;
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riscv,max-priority = <3>;
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riscv,ndev = <32>;
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};
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clint: clint@f8b00000 {
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compatible = "sifive,clint0";
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interrupts-extended = <&hlic 3 &hlic 7>;
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reg = <0xf8b00000 0x10000>;
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};
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timer0: timer@e0002800 {
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compatible = "efinix,sapphire-timer0";
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reg = <0xe0002800 0x40>;
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interrupt-parent = <&plic0>;
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interrupts = <19 0>;
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status = "disabled";
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};
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gpio0: gpio@f8015000 {
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compatible = "efinix,sapphire-gpio";
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reg = <0xf8015000 0x100>;
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reg-names = "base";
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ngpios = <4>;
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gpio-controller;
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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};
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uart0: uart@f8010000 {
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compatible = "efinix,sapphire-uart0";
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interrupt-parent = <&plic0>;
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interrupts = <1 1>;
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reg = <0xf8010000 0x40>;
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reg-names = "base";
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current-speed = <115200>;
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status = "disabled";
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};
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};
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};
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