zephyr/soc/x86/ia32/dts_fixup.h

31 lines
1.3 KiB
C

/* SoC level DTS fixup file */
#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_3F8_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_3F8_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_3F8_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_3F8_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_3F8_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_3F8_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_3F8_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR NS16550_2F8_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_2F8_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_2F8_LABEL
#define CONFIG_UART_NS16550_PORT_1_IRQ NS16550_2F8_IRQ_0
#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_2F8_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS NS16550_2F8_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ NS16550_2F8_CLOCK_FREQUENCY
#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE
#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE
#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS
/* End of SoC Level DTS fixup file */