114 lines
3.3 KiB
C
114 lines
3.3 KiB
C
/*
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_FLASH_XSPI_STM32_H_
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#define ZEPHYR_DRIVERS_FLASH_XSPI_STM32_H_
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/* Macro to check if any xspi device has a domain clock or more */
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#define STM32_XSPI_DOMAIN_CLOCK_INST_SUPPORT(inst) \
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DT_CLOCKS_HAS_IDX(DT_INST_PARENT(inst), 1) ||
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#define STM32_XSPI_INST_DEV_DOMAIN_CLOCK_SUPPORT \
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(DT_INST_FOREACH_STATUS_OKAY(STM32_XSPI_DOMAIN_CLOCK_INST_SUPPORT) 0)
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/* This symbol takes the value 1 if device instance has a domain clock in its dts */
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#if STM32_XSPI_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32_XSPI_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define STM32_XSPI_DOMAIN_CLOCK_SUPPORT 0
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#endif
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#define STM32_XSPI_FIFO_THRESHOLD 4U
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/* Valid range is [0, 255] */
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#define STM32_XSPI_CLOCK_PRESCALER_MIN 0U
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#define STM32_XSPI_CLOCK_PRESCALER_MAX 255U
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#define STM32_XSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / ((prescaler) + 1U))
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/* Max Time value during reset or erase operation */
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#define STM32_XSPI_RESET_MAX_TIME 100U
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#define STM32_XSPI_BULK_ERASE_MAX_TIME 460000U
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#define STM32_XSPI_SECTOR_ERASE_MAX_TIME 1000U
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#define STM32_XSPI_SUBSECTOR_4K_ERASE_MAX_TIME 400U
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#define STM32_XSPI_WRITE_REG_MAX_TIME 40U
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/* used as default value for DTS writeoc */
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#define SPI_NOR_WRITEOC_NONE 0xFF
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#if STM32_XSPI_USE_DMA
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/* Lookup table to set dma priority from the DTS */
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static const uint32_t table_priority[] = {
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DMA_LOW_PRIORITY_LOW_WEIGHT,
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DMA_LOW_PRIORITY_MID_WEIGHT,
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DMA_LOW_PRIORITY_HIGH_WEIGHT,
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DMA_HIGH_PRIORITY,
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};
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/* Lookup table to set dma channel direction from the DTS */
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static const uint32_t table_direction[] = {
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DMA_MEMORY_TO_MEMORY,
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DMA_MEMORY_TO_PERIPH,
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DMA_PERIPH_TO_MEMORY,
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};
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struct stream {
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DMA_TypeDef *reg;
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const struct device *dev;
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uint32_t channel;
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struct dma_config cfg;
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uint8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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};
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#endif /* STM32_XSPI_USE_DMA */
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typedef void (*irq_config_func_t)(const struct device *dev);
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struct flash_stm32_xspi_config {
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const struct stm32_pclken *pclken;
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size_t pclk_len;
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irq_config_func_t irq_config;
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size_t flash_size;
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uint32_t max_frequency;
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int data_mode; /* SPI or QSPI or OSPI */
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int data_rate; /* DTR or STR */
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const struct pinctrl_dev_config *pcfg;
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#if STM32_XSPI_RESET_GPIO
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const struct gpio_dt_spec reset;
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#endif /* STM32_XSPI_RESET_GPIO */
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};
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struct flash_stm32_xspi_data {
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/* XSPI handle is modifiable ; so part of data struct */
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XSPI_HandleTypeDef hxspi;
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struct k_sem sem;
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struct k_sem sync;
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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struct flash_pages_layout layout;
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#endif
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struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES];
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/* Number of bytes per page */
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uint16_t page_size;
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/* Address width in bytes */
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uint8_t address_width;
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/* Read operation dummy cycles */
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uint8_t read_dummy;
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uint32_t read_opcode;
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uint32_t write_opcode;
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enum jesd216_mode_type read_mode;
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enum jesd216_dw15_qer_type qer_type;
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#if defined(CONFIG_FLASH_JESD216_API)
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/* Table to hold the jedec Read ID given by the octoFlash const */
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uint8_t jedec_id[JESD216_READ_ID_LEN];
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#endif /* CONFIG_FLASH_JESD216_API */
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int cmd_status;
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#if STM32_XSPI_USE_DMA
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struct stream dma_tx;
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struct stream dma_rx;
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#endif /* STM32_XSPI_USE_DMA */
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};
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#endif /* ZEPHYR_DRIVERS_FLASH_XSPI_STM32_H_ */
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