Only toggle the hw cs if the cs is not set as a gpio. SPI trancieve
should also return the rx len when in slave configuration.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This cleans up the instantiation macro. DBG_COUNTER was also removed
as that appears to be unnecessary. This also allows for if it is a
serial target to be configured from the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
The HAS_SPI_DW Kconfig is rather unncessary. If the synopsys designware
spi is to be included. It should come from the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
In sdhc_spi_response_get, the logic for slow cards previously only
retried reads 16 times. Instead of using this approach, read from the
card every 10 ms until the command timeout is reached or it responds.
This way, the command timeout will be respected for cards that do not
respond.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds test for clock_getcpuclockid() to
make sure clock_id is equal to CLOCK_PROCESS_CPUTIME_ID
after a successful call
Fixes#59954
Signed-off-by: Jai Arora <infolinesoni@gmail.com>
Adding driver for GC9A01A 240x240 based LCD displays.
Should be working with GC9C01 as well (untested).
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Create a separate ZTEST_SUITE() to properly manage resources
that are shared between test cases. Add some assertions where
they were missing.
Additionally, we don't need verbose printing in this testsuite,
so change `printk()` to `LOG_DBG()`
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Reduces the number of seconds that the test runs to 15 seconds
(down from 30 seconds). This should still be sufficient time
to determine if there is anything amiss with the synchonous
thread suspend/resume. Furthermore, the test itself has been
tagged as being slow and its timeout increased to 10 minutes
(600 seconds) as some simulators are rather slow.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
rssi 31 will be -51dBm or greater, where -51 is valid. Fix the
range by allowing until -51.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
* Internal Clock not getting stable during initialization
* SD clock was not enabled
* Removed duplicate file.
* Removed write to readonly registers
* Moved function pointer structure from data section to RO section
* Wrong macro names
* Refactoring of lower layer header file.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Some definitions were only used in soc.c, there's no need to expose them
in a public header like soc.h.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
<soc.h> is needed to pull some APIs defined in soc.h.
<fsl_device_registers.h> is needed to access EVENT0/1 addresses.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
FU540 SoC has 16 GPIOs, this way, the GPIO API can perform correct
asserts when a pin is provided. Note that default is 32, correct for eg
FE310.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
It looks like some soc_offsets.h files need to be included before
kernel_offsets, otherwise there are some header race conditions due to
the infamous soc.h. This problem is exposed if all soc.h are removed
from RISC-V arch header files (see the upcoming commits). It can be
reproduced by building rv32m1_vega_ri5cy board after applying all the
patches in this series (excluding this one, of course).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add test for `display_read()` and `display_write()` api.
Note: The CI environment has no display device, which makes it fail
the tests. So, I make this test case `build_only`. But it can run in
a display device available environment.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Fixed an issue where `display_read()` in the SDL driver was not working.
In the current implementation, use texture to represent screen images.
To read this, draw it once on another surface and then read it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add SDL_DISPLAY_USE_HARDWARE_ACCELEREATOR to be able to switch
enable/disable hardware accelerator.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Changes:
* Fixed typo in the PWM channel number (32 -> 3)
* Added a prescaler to make the board compatible
with the blinky_pwm sample
Output of the sample before the fix:
PWM-based blinky
Calibrating for channel 32...
[00:00:00.010,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.016,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.022,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.028,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.034,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.040,000] <err> pwm_stm32: Invalid channel (32)
Error: PWM device does not support a period at least 31250000
After the fix:
PWM-based blinky
Calibrating for channel 3...
Done calibrating; maximum/minimum periods 1000000000/7812500 nsec
Presence of PWM signal after the fix
has been confirmed using a logic analyzer.
Signed-off-by: Maksim Salau <maksim.salau@gmail.com>
Ryan McClelland