The RISC-V FPU context switching code is intricate and sometimes subtle.
Here's a test that exercizes various code paths to ensure they work as
intended, and to confirm that the target hardware does behave as
expected too.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Some implementations may not capture the faulting instruction in mtval
and set it to zero when an illegal instruction fault is raised This is
notably the case with QEMU version 7.0.0 when a CSR instruction is
involved.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The FRCSR, FSCSR, FRRM, FSRM, FSRMI, FRFLAGS, FSFLAGS and FSFLAGSI
are in fact CSR instructions targeting the fcsr, frm and fflags
registers. They should be caught as FPU instructions as well.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
- IRQ state for the interrupted context corresponds to the PIE bit not
the IE bit.
- Restoring the saved FPU state should clear the entire field before
or'ing wanted bits in.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
With all of the test suite issues on this board fixed, qemu_x86_tiny should
now be usable with picolibc.
Signed-off-by: Keith Packard <keithp@keithp.com>
This test has trouble on qemu_x86_tiny and randomly generates a Double
Fault error. I couldn't get it to reliably run with picolibc as a Double
Fault usually occured before the test completed.
I spent a couple of hours attempting to track this down and found that it
happens when code pages for the main thread get unmapped because the
qemu_x86_tiny intentionally offers very few available PTEs.
Work around this by just using the minimal libc for this test.
Signed-off-by: Keith Packard <keithp@keithp.com>
Add another clause in the test_ram_perms code to verify that any pinned
regions have the correct flags.
Signed-off-by: Keith Packard <keithp@keithp.com>
When there's no malloc heap needed for picolibc, don't reserve
the page frames that would be needed. This makes sure
the kernel.demand_paging tests provoke the page faults as
expected.
Signed-off-by: Keith Packard <keithp@keithp.com>
For RISC-V, the reg property of a cpu node in the devicetree describes
the low level unique ID of each hart. Using devicetree macro's, a list
of all cpus with status "okay" can be generated.
Using devicetree overlays, a hart or multiple harts can be marked as
"disabled", thus excluding them from the list. This allows platforms
that have non-zero indexed SMP capable harts to be functionally mapped
to Zephyr's sequential CPU numbering scheme.
On kernel init, if the application has MP_MAX_NUM_CPUS greater than 1,
generate the list of cpu nodes from the device tree with status "okay"
and map the unique hartid's to zephyr cpu's
While we are at it, as the hartid is the value that gets passed to
z_riscv_secondary_cpu_init, use that as the variable name instead of
cpu_num
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
RISC-V multi-hart systems that employ a heterogeneous core complex are
not guaranteed to have the smp capable harts starting with a unique id
of zero, matching Zephyr's sequential zero indexed cpu numbering scheme.
Add option, RV_BOOT_HART to choose the hart to boot from.
On reset, check the current hart equals RV_BOOT_HART: if so, boot first
core. else, loop in the boot secondary core and wait to be brought up.
For multi-hart systems that are not running a Zephyr mp or smp
application, park the non zephyr related harts in a wfi loop.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Fix a build error when the driver is built with:
CONFIG_PM=y
CONFIG_PM_DEVICE=n
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
due to uart_xec_pm_policy_state_lock_get() and rx_refresh_timeout_work()
declared under different configuration options.
Fixes: 343d1919f1 "uart: microchip: add low power & wake support"
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
To follow the IWDG configuration sequence, the timeout install is
just preparing the reload and prescaler parameters.
Then during the iwdg setup the watchdog is enabled and configured
at the same time.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
These tests test the basic functionality of creating
object and resource instances, setting buffers, writing
and reading to and from resources, and setting and triggering
callbacks.
Signed-off-by: Jarno Lämsä <jarno.lamsa@nordicsemi.no>
`ad_len` was never initiatialized before we started
incremetenting and using it.
We would also override any user data in ad_init, which
is fixed by using the length of the user data as an
offset into the array.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
Using the same memory as a user data pointer and FIFO reserved space
could lead to a crash in certain circumstances, those two use cases were
not completely separate.
The crash could happen for example, if an incoming TCP connection was
abruptly closed just after being established. As TCP uses the user data
to notify error condition to the upper layer, the user data pointer
could've been used while the newly allocated context could still be
waiting on the accept queue. This damaged the data area used by the FIFO
and eventually could lead to a crash.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
1. Do not copy over the data to the local buffer,
it can be directly sent to the controller. The
cache is flushed before calling the HAL send
function. Also do not allocate a buffer from
the heap pool for the write operation.
2. Remove a length check as this is handled by
the HAL driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
If errors are found and tests are failing, print a brief summary showing
the top 10 items failing with instructions on how to reproduce either
with twister or west.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This will allow something like this:
west build -b qemu_x86 -T samples/hello_world/sample.basic.helloworld
instead of:
cd samples/hello_world
west build -b qemu_x86 -T sample.basic.helloworld
Using this option will allow to take twister output and just pass it to
west to reproduce failures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Fixes issue where a build warning would be emmited for sockets_tls.c due
to usage of the deprecated fcntl.h header file.
Signed-off-by: Jared Baumann <jared.baumann8@t-mobile.com>
Currently if C11 or higher is enabled, many files fail to compile because
static_assert is defined in multiple header files. Solve this by
disabling the one in the HAL if the other macro is found
Signed-off-by: Thad House <thadhouse1@gmail.com>
Add a note on requirements for runners that they be OS agnostic
and not assume a specific device or udev rule determines one
exact device.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add test of the GPIO hog functionality using the optional GPIO APIs for
getting pin direction and configuration.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for automatically configuring GPIO hogs defined in the
devicetree during system initialization.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Existence of enabled GPIO hog nodes cannot be determined using any of the
existing kconfig functions. Add custom kconfig helper function to determine
whether any GPIO hogs nodes are enabled.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
GPIO hog nodes contain a "gpios" property, but unlike other "*-gpios"
properties, these are not phandle-arrays as they only carry the data part
(e.g. pin, flags) but lack the phandles to the (parent) GPIO controller.
Add special devicetree tooling to handle the "gpios" property of GPIO hog
nodes and generate special devicetree helper macros as if they were phandle
arrays.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Each GPIO controller may contain GPIO hog definitions. GPIO hogging is a
mechanism for providing automatic GPIO configuration during system
initialization.
Each GPIO hog is represented as a child node of the GPIO controller.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add a new macro, IS_PTR_ALIGNED_BYTES() that verifies if a pointer
is aligned against a specific byte boundary supplied as argument.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
It is not guaranteed that a multi-core RISC-V hart numbering scheme
will match Zephyr's sequential cpu numbering scheme. Read the hartid and
use that value in calculation to get mtime_cmp reg, instead of the
current_cpu id.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
changes to support low power and wake support in microchip xec uart
driver. Add support for wakerx_gpio config in dts to select the wake gpio.
Configure for wake in PM_DEVICE_ACTION_SUSPEND state and clear
interrupt in wake isr. Also added support for
CONFIG_UART_CONSOLE_INPUT_EXPIRED
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The AN547 no longer functions with this TF-M sample, and has been
broken since TF-M 1.6.0 without CI catching the issue, since this sample
wasn't modified to cause a CI run on the affected target.
Removing this board from the sample until the board support can be
reworked.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
Update TF-M secure partition sample for TF-M 1.7.0.
Removes the support for Library model in the sample.
Updates to using PSA framework 1.1.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Signed-off-by: David Brown <david.brown@linaro.org>
Add TF-M connection based NCS API source file to build.
This file is needed when a secure service is using connection
based method.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Signed-off-by: David Brown <david.brown@linaro.org>
Update the sample to be compatible with API changes introduced in
TF-M 1.7.0, adding a new direct call to the PSA Crypto API to generate
random data, and cleaning up existing functions for compatibility
sake.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
Removes the `psa_crypto` sample from the current release, due to
PSA API conflicts that can not be immediately resolved between Zephyr's
instance of MbedTLS in the NS environment, and the TF-M PSA APIs
included when building with TF-M support.
PSA API changes upstream in MbedTLS 3.2.1 (used by TF-M 1.7.0), and
MbedTLS 3.1 (used in TF-M 1.6.0) need to be be resolved in both
upstream projects before this sample can be reintroduced.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
Removes the `psa_firmware` sample, which is based on an older version
(0.7) of the FWU service from TF-M 1.6.0. This sample needs to be
refactored to use FWU 1.0, included in TF-M 1.7.0 and future releases.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
Andrei Emeltchenko