The docstring for this function states that it is guaranteed to perform
a copy byte by byte, but this is not true in general without a
`volatile` storage type on the casted pointer.
Signed-off-by: Chris McDonald <cjmcdonald@chromium.org>
Disabling clock may conflict with concurrent usage of GPIOs and pins in
AF mode. This can be improved once a proper clock control API is in
place.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT overlay to run gpio_basic_api test on GD32F403Z-EVAL board. In
order to make testing easy a couple of accessible pins have been
selected: PD0 and PD1 pins exposed via P3 and P2 respectively.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT overlay to run gpio_basic_api test on GD32F450I-EVAL board. In
order to make testing easy a couple of accessible pins have been
selected: PC6 and PC7, the last 2 pins on the DCI camera 2.54" header.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add definitions for board LEDs and keys now that a GPIO driver exists.
The GPIO driver has also been enabled in the board defconfig, since it
is required to run some basic samples (e.g. blinky).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add definitions for board LEDs and keys now that a GPIO driver exists.
The GPIO driver has also been enabled in the board defconfig, since it
is required to run some basic samples (e.g. blinky).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add GPIO driver for Gigadevice SoCs. The driver supports devices with
the AF and AFIO models.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
- The gpio dt-bindings were not included
- gpio-controller property was not present in gpio nodes
- number of gpio cells was not present in gpio nodes
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add initial support for the GigaDevice External Interrupt Controller.
This driver is required to manage GPIO interrupts. Only EXTI lines 0 to
15 are supported for now (no LVD, RTC, etc.). Driver can be extended in
the future to add support for extra EXTI lines.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add DT node for EXTI (External Interrupt Controller). Only line
interrupts added for now (used for GPIO interrupts).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The nucleo_h743 allows extra capes to extend its functionality.
In our case it has been extended to use 32MiB SPI-NOR memory
connected to QUADSPI dedicated pins from block2.
Moreover, upper 16MiB of SPI-NOR memory has been used to store
littlefs data to test 4B addressing mode (which may cause problems
when NOR-flash is larger than 16 MiB).
Now the littlefs sample can be used to test this extension:
west build -p always -b nucleo_h743zi ./zephyr/samples/subsys/fs/littlefs
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change provides support for 4 IO read (via 4READ command) and
program (via 4PP). Flash memory pins SIO[0123], CLK and CS are used.
All of them are controlled by stm32 QSPI IP block.
The instruction code for fast reading as well as number of latency
cycles required are read from SFDP structure provided by flash memory.
The number of required read latency cycles when performing reading
is the sum of SPI-NOR memory mode bits and wait states (also named
as 'dummy cycles').
It also has been assumed that memory, which supports fast read (4READ),
also will support fast programming (4PP command) as this information is
not available in SFDP.
One also need to enable the QUAD IO support in board's device tree by
defining 'spi-bus-width = <4>' property. It is required as it may
happen that not all QSPI dedicated pins are used (for example only two
of them are available).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
For proper operation of QUADSPI IP block, both sides of communication;
NOR flash memory and STM32 controller need to support 4 IO
transmission.
After this change the QSPI stm32 driver is able to program NOR flash
memory to switch itself to use all 4 IO lines (SIO[0123]) to transmit
and receive data.
The QE bit (in SPI-NOR's Status Register) is the non-volatile one, so
setting it is done only once (at first boot of the device).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit provides define for reading the control register (CR) on
the flash memory.
In that register the information about 4B addressing is stored.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The spi-bus-width property provides information if the target system
has all SIO[0123] pins connected to NOR flash memory.
It must be equal to 4 to enable QSPI 4 IO operation.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Some flash memories connected to QUADSPI IP block on stm32[fh]7 devices
require proper reset pulse before configuration.
This patch adds two new properties - the 'reset-gpios' phandle,
which allows specifying GPIO pin for RESETn pulse and
'reset-gpios-duration', which provides the time (in ms) for reset
duration.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The 'flash-id' property defines the number of QSPI's dedicated GPIO
bank (and flash ID), which will be used to communicate with flash
memory.
For example, on stm32h7xx it is possible to use 'quadspi_bk1_*' and
'quadspi_bk2_*' set of pins, so one may need to select between them
when required.
By default - pins from 'quadspi_bk1_*' bank are used, so the
'flash-id = <2>;' property, when your use case (e.g. PCB design)
requires it, forces usage of 'quadspi_bk2_*' pins.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Now in Zephyr only stm32f7 processors have by default provided support
for QSPI IP block.
The same IP block is also available in stm32h7 (with different offsets),
so proper DTS description shall be provided as well for it.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The stm32 HAL code for qspi (SHA1: 5c8275071ec1cf160bfe8c18bbd93):
stm32cube/stm32h7xx/drivers/src/stm32h7xx_hal_qspi.c implicitly
depends on the stm32h7xx_hal_mdma.c driver as it uses unconditionally
'HAL_MDMA_Abort_IT()' function.
To avoid build breaks - no matter if QSPI IP block works with DMA
or interrupts - the CONFIG_USE_STM32_HAL_MDMA shall be defined.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
In npcx_itim_evt_isr, it updates the cyc_sys_announced variable and
then calls sys_clock_announce() to update the kernel curr_tick variable.
If an ISR handler with higher priority preempts the timer ISR after the
sys_clock_announce is updated and before the sys_clock_announce() is
called, it will read the wrong time when calling k_uptime_get() because
the cyc_sys_announced and the curr_tick are not synchronized.
The commit fixes the problem by raising the timer's interrupt priority
to the highest one (i.e. 1 in npcx's configuration).
This commit also moves the computation of the delta cycle inside the
spinlock in sys_clock_elapsed() to prevent another potential racing
condition.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Fix wrong extra_args definitions wich cause that this args were not used
by CMake during building this samples via Twister in CI.
Signed-off-by: Piotr Golyzniak <piotr.golyzniak@nordicsemi.no>
Add emulated CAN loopback device. The device is disabled by default
since a loopback-only device is not suitable for all use cases/test
cases.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Convert the CAN loopback driver from being configured via Kconfig to
multi-instance configured via devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The notification is sent after the subsystem select the power state to
use and after suspend devices. The callback should not try to access a
device. In this case, uart through LOG macros.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
gsm_ppp_stop should cancel possible running work items.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Wouter Cappelle <wouter.cappelle@crodeon.com>
The 'work' argument of a delayable work's handler should be
converted to delayable work before passing into the CONTAINER_OF
macro.
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Tag can be changed at runtime. Feature is enabled by setting
maximum tag length to positive value. Additionally, default
tag can be configured in Kconfig.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
The syscall_perf test cannot be built successfully due to region RAM
overflow on qemu_riscv32_xip and hifive1_revb. The dtim is only 16KB,
To reduce the main stack size to make it can be built successfully.
Base on the spec(fe310-g002-manual-v1p1.pdf), the size of itim should
be 8KB. Modify the definition in its DTS file.
And it also fix some of the gcc warning when testing it by twister.
This PR partially fixes#41399.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The vnd,gpio-device compatible is now used by the test GPIO driver
(CONFIG_GPIO_TEST) introduced in #41387. This means that we can't define
new devices with this compatible when CONFIG_GPIO=y.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Set TF-M option for nordic HAL library path to use the included
nordic HAL instead of the version that TF-M downloads.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Fixing code coverage data cannot be generated correctly when running
tests/benchmark/latency_measure test suite. This is because the gcov
data do not generate completely when the measuring thread stop. So
our solution is:
In main(), just waiting for the measuring thread to complete before
the gcov data start to dump out, to make sure all the gcov data can
be output completely.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Move z_priq_mq_add and z_priq_mq_remove into #ifdef CONFIG_SCHED_MULTIQ
block, because they are only used with that config.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
This commit aligns nrf_802154_lp_timer_zephyr platform to new API of
nrf_rtc_timer. Moreover, it implements lp_timer synchronization
functions using the new nrf_rtc_timer API.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Signed-off-by: Paweł Kwiek <pawel.kwiek@nordicsemi.no>
This commit introduces the following changes:
* nrf_rtc_timer is extended with a capability to handle RTC overflow,
allowing it to operate on absolute RTC ticks, rather than relative
ticks.
* overflow handling is ZLI-proof and relies on the sys clock
handler being executed twice every RTC counter's overflow.
* callbacks are given an absolute RTC tick value as a parameter instead
of CC register's value. The absolute RTC tick value is the RTC counter
value set during CC channel configuration extended to 64 bits.
* in case the timer's target time is in the past or is the current tick,
the timer fires as soon as possible, however still from the RTC's ISR
context.
* in case an active timer is set again with the same target time, it is
not scheduled again - only its event data is updated. Otherwise, the
timer is scheduled as usual.
* a scheduled timer can be aborted.
* system clock functions are now using 64 bit values internally.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Signed-off-by: Jedrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Signed-off-by: Paweł Kwiek <pawel.kwiek@nordicsemi.no>
Chris McDonald