- Modify the macro in source code AGT to get the right data from
device tree
- Modify name of agt node
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
These properties should eventually be removed from this binding as they
have been introduced to control soc specific clock trees and don't
correlate to anything in the IP, but for now just make them not required
and remove them from DT for SOCs that don't even use them.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
PR #79683 missed a few nodes introduced while it was under review.
Replace the remaining raw values with STM32_CLOCK in WB0 DTSI files.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Only initialize the HFXO Manager HAL driver if the HFXO is enabled in
DeviceTree, the device uses SYSRTC for timekeeping, and Power Manager
is enabled. HFXO Manager integrates with the Sleeptimer HAL driver for
SYSRTC to autonomously wake the HFXO prior to Sleeptimer wakeup from
deep sleep. It is not needed on devices that don't have HFXO-SYSRTC
integration, and it is not needed if the application doesn't use deep
sleep.
Add missing call to init_hardware() prior to init().
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Additional IO ports (6,7 and 8) are availble on the r7fa6m4af3cfb
variant of the RA6M4 Microcontroller.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
The peer remote device "source_dev" can be retrieved from the
remote-endpoint-label. Direct reference via phandle is not needed.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Instead of fixing csi2rx clock frequencies, set them according to the
pixel rate got from the camera sensor.
Signed-off-by: Trung Hieu Le <trunghieu.le@nxp.com>
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
USB configuration is missing in Devicetree for NXP MCX C series.
Add the configuration to common and SoC specific dtsi file.
Delete usb node for SoCs without USB support.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Add stm32h7 ethernet compatible "st,stm32h7-ethernet",
used also for stm32h5.
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
The DT node "stimer0" represented two different hardware timers,
RTCC and SYSRTC. Use the correct peripheral names for the nodes.
Add interrupt names and missing interrupt numbers.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add a pinctrl driver for Microchip MEC5 HAL based chips.
The driver removes the YAML enum "no change" property
value from the driver strength and slew rate properties.
Update the shared header file in mec soc common folder to
use a different Z_PINCTRL_STATE_PINCFG_INIT for MEC5.
Modifications to legacy MEC172x XEC PINCTRL will be in
a future PR.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Die temperature measurement is not configured in devicetree
for NXP MCX C series.
Add die temperature measurement configuration.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Rename the Silabs HCI driver to hci_silabs_efr32.c to better indicate what
hardware it supports. Also rename the associated devicetree binding and
Kconfig options to be consistent with the new driver name.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add initial SoC support for the TI J721E SoC series Cortex-R5 core.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Introduce bindings for Series 2 oscillators: HFRCODPLL, HFRCOEM23,
LFRCO and LFXO.
Add clock tree representation in devicetree `clocks` node.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Switch EFR32MG21 to use the device init HAL. This makes the init sequence
the same as the rest of Series 2.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The DC-DC converter was unconditionally initialized with default
settings on Series 2. Add device tree binding and nodes, and guard
call to init function. Map DT options to config header from HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Added a new driver to support SPI communication via EUSART. Since the
Silabs EFR32MG24 family SoCs have only one USART, EUSART support is
necessary for implementing SPI functionality.
Signed-off-by: Teresa Zepeda Ventura <teresa.zvent@gmail.com>
- boards: renesas: Add support for agt.
- drivers: counter: Add support for counter driver use agt
- dts: arm: Add support for agt.
- dts: bindings: Add support for agt counter driver.
- soc: renesas: Add support for agt counter driver.
- samples: drivers: counter: alarm: Add support for RA8
This is initial support with only basic functionality for counter
operation on Zephyr using AGT hardware, current support for
count source is limited to LOCO and PCLKB, other count source
like underflow signal external pin or AGTIO from another AGT
channel will be added in later support
Signed-off-by: Ha Nguyen <ha.nguyen.fz@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add 1-Wire register file
Some MAX32 MCUs has 1-Wire peripheral some one not
So that added in device related dtsi file.
Has 1-W Not have 1-W
MAX32655 MAX32662
MAX32666 MAX32670
MAX32680 MAX32672
MAX32690 MAX32675
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
Gerard Marull-Paretas