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drivers: spi: Add SPI device support for Apollo3 SoCs 

This commit adds spi device support for Apollo3 SoCs.

Signed-off-by: Hao Luo <hluo@ambiq.com>
This commit is contained in:
Hao Luo 2024-08-02 17:01:41 +08:00 committed by Henrik Brix Andersen
parent c2b6bcc660
commit 1e5cdb110a
10 changed files with 506 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi
View File

@ -65,7 +65,11 @@
bias-pull-up;
};
};
spid0_default: spid0_default {
group1 {
pinmux = <SLSCK_P0>, <SLMISO_P2>, <SLMOSI_P1>, <SLNCE_P3>;
};
};
spi0_default: spi0_default {
group1 {
pinmux = <M0SCK_P5>, <M0MISO_P6>, <M0MOSI_P7>;

6
boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi
View File

@ -65,7 +65,11 @@
bias-pull-up;
};
};
spid0_default: spid0_default {
group1 {
pinmux = <SLSCK_P0>, <SLMISO_P2>, <SLMOSI_P1>, <SLNCE_P3>;
};
};
spi0_default: spi0_default {
group1 {
pinmux = <M0SCK_P5>, <M0MISO_P6>, <M0MOSI_P7>;

3
drivers/spi/CMakeLists.txt
View File

@ -46,7 +46,8 @@ zephyr_library_sources_ifdef(CONFIG_SPI_PW spi_pw.c)
zephyr_library_sources_ifdef(CONFIG_SPI_SMARTBOND spi_smartbond.c)
zephyr_library_sources_ifdef(CONFIG_SPI_OPENTITAN spi_opentitan.c)
zephyr_library_sources_ifdef(CONFIG_SPI_NUMAKER spi_numaker.c)
zephyr_library_sources_ifdef(CONFIG_SPI_AMBIQ spi_ambiq.c)
zephyr_library_sources_ifdef(CONFIG_SPI_AMBIQ_SPIC spi_ambiq_spic.c)
zephyr_library_sources_ifdef(CONFIG_SPI_AMBIQ_SPID spi_ambiq_spid.c)
zephyr_library_sources_ifdef(CONFIG_SPI_AMBIQ_BLEIF spi_ambiq_bleif.c)
zephyr_library_sources_ifdef(CONFIG_SPI_RPI_PICO_PIO spi_rpi_pico_pio.c)
zephyr_library_sources_ifdef(CONFIG_SPI_MCHP_MSS spi_mchp_mss.c)

24
drivers/spi/Kconfig.ambiq
View File

@ -6,21 +6,21 @@
# SPDX-License-Identifier: Apache-2.0
#
menuconfig SPI_AMBIQ
bool "AMBIQ SPI driver"
menuconfig SPI_AMBIQ_SPIC
bool "AMBIQ SPI Controller driver"
default y
depends on DT_HAS_AMBIQ_SPI_ENABLED
select GPIO
select AMBIQ_HAL
select AMBIQ_HAL_USE_SPI
select AMBIQ_HAL_USE_SPIC
help
Enable driver for Ambiq SPI.
Enable driver for Ambiq SPI in Controller mode.
if SPI_AMBIQ
if SPI_AMBIQ_SPIC
config SPI_AMBIQ_DMA
bool "AMBIQ APOLLO SPI DMA Support"
depends on SPI_AMBIQ
depends on SPI_AMBIQ_SPIC
help
Enable DMA for Ambiq SPI.
@ -31,7 +31,17 @@ config SPI_DMA_TCB_BUFFER_SIZE
help
DMA Transfer Control Buffer size in words
endif # SPI_AMBIQ
endif # SPI_AMBIQ_SPIC
config SPI_AMBIQ_SPID
bool "AMBIQ SPI Device driver"
default y
depends on DT_HAS_AMBIQ_SPID_ENABLED
select GPIO
select AMBIQ_HAL
select AMBIQ_HAL_USE_SPID
help
Enable driver for Ambiq SPI in Device mode.
config SPI_AMBIQ_BLEIF
bool "AMBIQ SPI-BLEIF driver"

5
drivers/spi/spi_ambiq.c → drivers/spi/spi_ambiq_spic.c
View File

@ -170,7 +170,7 @@ static int spi_config(const struct device *dev, const struct spi_config *config)
}
if (config->operation & SPI_OP_MODE_SLAVE) {
LOG_ERR("Slave mode not supported");
LOG_ERR("Device mode not supported");
return -ENOTSUP;
}
if (config->operation & SPI_MODE_LOOP) {
@ -183,7 +183,8 @@ static int spi_config(const struct device *dev, const struct spi_config *config)
return -ENOTSUP;
}
/* Select slower of two: SPI bus frequency for SPI device or SPI master clock frequency */
/* Select slower of two: SPI bus frequency for SPI device or SPI controller clock frequency
*/
data->iom_cfg.ui32ClockFreq =
(config->frequency ? MIN(config->frequency, cfg->clock_freq) : cfg->clock_freq);
ctx->config = config;

430
drivers/spi/spi_ambiq_spid.c Normal file
View File

@ -0,0 +1,430 @@
/*
* Copyright (c) 2024 Ambiq <www.ambiq.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_spid
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_ambiq_spid);
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#include <zephyr/pm/device_runtime.h>
#include <stdlib.h>
#include <errno.h>
#include "spi_context.h"
#include <am_mcu_apollo.h>
#define AMBIQ_SPID_PWRCTRL_MAX_WAIT_US 5
typedef int (*ambiq_spi_pwr_func_t)(void);
struct spi_ambiq_config {
const struct gpio_dt_spec int_gpios;
uint32_t base;
int size;
const struct pinctrl_dev_config *pcfg;
ambiq_spi_pwr_func_t pwr_func;
void (*irq_config_func)(void);
};
struct spi_ambiq_data {
struct spi_context ctx;
am_hal_ios_config_t ios_cfg;
void *ios_handler;
int inst_idx;
struct k_sem spim_wrcmp_sem;
};
#define AMBIQ_SPID_TX_BUFSIZE_MAX 1023
uint8_t ambiq_spid_sram_buffer[AMBIQ_SPID_TX_BUFSIZE_MAX];
#define AMBIQ_SPID_DUMMY_BYTE 0
#define AMBIQ_SPID_DUMMY_LENGTH 16
static uint8_t ambiq_spid_dummy_buffer[2][AMBIQ_SPID_DUMMY_LENGTH];
#define AMBIQ_SPID_WORD_SIZE 8
#define AMBIQ_SPID_FIFO_BASE 0x78
#define AMBIQ_SPID_FIFO_END 0x100
#define AMBIQ_SPID_FIFO_LENGTH (AMBIQ_SPID_FIFO_END - AMBIQ_SPID_FIFO_BASE)
#define AMBIQ_SPID_INT_ERR (AM_HAL_IOS_INT_FOVFL | AM_HAL_IOS_INT_FUNDFL | AM_HAL_IOS_INT_FRDERR)
#define AMBIQ_SPID_XCMP_INT \
(AM_HAL_IOS_INT_XCMPWR | AM_HAL_IOS_INT_XCMPWF | AM_HAL_IOS_INT_XCMPRR | \
AM_HAL_IOS_INT_XCMPRF)
static void spi_ambiq_reset(const struct device *dev)
{
struct spi_ambiq_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
/* cancel timed out transaction */
am_hal_ios_disable(data->ios_handler);
/* NULL config to trigger reconfigure on next xfer */
ctx->config = NULL;
/* signal any thread waiting on sync semaphore */
spi_context_complete(ctx, dev, -ETIMEDOUT);
}
static void spi_ambiq_inform(const struct device *dev)
{
const struct spi_ambiq_config *cfg = dev->config;
/* Inform the controller */
gpio_pin_set_dt(&cfg->int_gpios, 1);
gpio_pin_set_dt(&cfg->int_gpios, 0);
}
static void spi_ambiq_isr(const struct device *dev)
{
uint32_t ui32Status;
struct spi_ambiq_data *data = dev->data;
am_hal_ios_interrupt_status_get(data->ios_handler, false, &ui32Status);
am_hal_ios_interrupt_clear(data->ios_handler, ui32Status);
if (ui32Status & AM_HAL_IOS_INT_XCMPWR) {
k_sem_give(&data->spim_wrcmp_sem);
}
}
static int spi_config(const struct device *dev, const struct spi_config *config)
{
struct spi_ambiq_data *data = dev->data;
struct spi_context *ctx = &(data->ctx);
int ret = 0;
data->ios_cfg.ui32InterfaceSelect = AM_HAL_IOS_USE_SPI;
if (spi_context_configured(ctx, config)) {
/* Already configured. No need to do it again. */
return 0;
}
if (SPI_WORD_SIZE_GET(config->operation) != AMBIQ_SPID_WORD_SIZE) {
LOG_ERR("Word size must be %d", AMBIQ_SPID_WORD_SIZE);
return -ENOTSUP;
}
if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
LOG_ERR("Only supports single mode");
return -ENOTSUP;
}
if (config->operation & SPI_LOCK_ON) {
LOG_ERR("Lock On not supported");
return -ENOTSUP;
}
if (config->operation & SPI_TRANSFER_LSB) {
LOG_ERR("LSB first not supported");
return -ENOTSUP;
}
if (config->operation & SPI_MODE_CPOL) {
if (config->operation & SPI_MODE_CPHA) {
data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_3;
} else {
data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_2;
}
} else {
if (config->operation & SPI_MODE_CPHA) {
data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_1;
} else {
data->ios_cfg.ui32InterfaceSelect |= AM_HAL_IOS_SPIMODE_0;
}
}
if (config->operation & SPI_OP_MODE_MASTER) {
LOG_ERR("Controller mode not supported");
return -ENOTSUP;
}
if (config->operation & SPI_MODE_LOOP) {
LOG_ERR("Loopback mode not supported");
return -ENOTSUP;
}
if (spi_cs_is_gpio(config)) {
LOG_ERR("CS control via GPIO is not supported");
return -EINVAL;
}
/* Eliminate the "read-only" section, so an external controller can use the
* entire "direct write" section.
*/
data->ios_cfg.ui32ROBase = AMBIQ_SPID_FIFO_BASE;
/* Making the "FIFO" section as big as possible. */
data->ios_cfg.ui32FIFOBase = AMBIQ_SPID_FIFO_BASE;
/* We don't need any RAM space, so extend the FIFO all the way to the end
* of the LRAM.
*/
data->ios_cfg.ui32RAMBase = AMBIQ_SPID_FIFO_END;
/* FIFO Threshold - set to half the size */
data->ios_cfg.ui32FIFOThreshold = AMBIQ_SPID_FIFO_LENGTH >> 1;
data->ios_cfg.pui8SRAMBuffer = ambiq_spid_sram_buffer,
data->ios_cfg.ui32SRAMBufferCap = AMBIQ_SPID_TX_BUFSIZE_MAX,
ctx->config = config;
ret = am_hal_ios_configure(data->ios_handler, &data->ios_cfg);
return ret;
}
static int spi_ambiq_xfer(const struct device *dev, const struct spi_config *config)
{
struct spi_ambiq_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
int ret = 0;
uint32_t chunk, num_written, num_read, used_space = 0;
while (1) {
/* First send out all data */
if (spi_context_tx_on(ctx)) {
spi_ambiq_inform(dev);
chunk = (ctx->tx_len > AMBIQ_SPID_TX_BUFSIZE_MAX)
? AMBIQ_SPID_TX_BUFSIZE_MAX
: ctx->tx_len;
am_hal_ios_fifo_space_used(data->ios_handler, &used_space);
/* Controller done reading the last block signalled
* Check if any more data available
*/
if (!used_space) {
if (ctx->tx_buf) {
/* Copy data into FIFO */
ret = am_hal_ios_fifo_write(data->ios_handler,
(uint8_t *)ctx->tx_buf, chunk,
&num_written);
} else {
uint32_t dummy_written = 0;
num_written = 0;
/* Copy dummy into FIFO */
while (chunk) {
uint32_t size = (chunk > AMBIQ_SPID_DUMMY_LENGTH)
? AMBIQ_SPID_DUMMY_LENGTH
: chunk;
ret = am_hal_ios_fifo_write(
data->ios_handler,
ambiq_spid_dummy_buffer[0], size,
&dummy_written);
num_written += dummy_written;
chunk -= dummy_written;
}
}
if (ret != 0) {
LOG_ERR("SPID write error: %d", ret);
goto end;
}
spi_context_update_tx(ctx, 1, num_written);
}
} else if (spi_context_rx_on(ctx)) {
/* Wait for controller write complete interrupt */
(void)k_sem_take(&data->spim_wrcmp_sem, K_FOREVER);
/* Read out the first byte as packet length */
num_read = am_hal_ios_pui8LRAM[0];
uint32_t size, offset = 0;
while (spi_context_rx_on(ctx)) {
/* There's no data in the LRAM any more */
if (!num_read) {
spi_ambiq_inform(dev);
goto end;
}
if (ctx->rx_buf) {
size = MIN(num_read, ctx->rx_len);
/* Read data from LRAM */
memcpy(ctx->rx_buf,
(uint8_t *)&am_hal_ios_pui8LRAM[1 + offset], size);
} else {
size = MIN(num_read, AMBIQ_SPID_DUMMY_LENGTH);
/* Consume data from LRAM */
memcpy(ambiq_spid_dummy_buffer[1],
(uint8_t *)&am_hal_ios_pui8LRAM[1 + offset], size);
}
num_read -= size;
offset += size;
spi_context_update_rx(ctx, 1, size);
}
} else {
break;
}
}
end:
if (ret != 0) {
spi_ambiq_reset(dev);
} else {
spi_context_complete(ctx, dev, ret);
}
return ret;
}
static int spi_ambiq_transceive(const struct device *dev, const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
const struct spi_buf_set *rx_bufs)
{
struct spi_ambiq_data *data = dev->data;
int ret;
if (!tx_bufs && !rx_bufs) {
return 0;
}
ret = pm_device_runtime_get(dev);
if (ret < 0) {
LOG_ERR("pm_device_runtime_get failed: %d", ret);
}
/* context setup */
spi_context_lock(&data->ctx, false, NULL, NULL, config);
ret = spi_config(dev, config);
if (ret) {
spi_context_release(&data->ctx, ret);
return ret;
}
spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
ret = spi_ambiq_xfer(dev, config);
spi_context_release(&data->ctx, ret);
/* Use async put to avoid useless device suspension/resumption
* when doing consecutive transmission.
*/
ret = pm_device_runtime_put_async(dev, K_MSEC(2));
if (ret < 0) {
LOG_ERR("pm_device_runtime_put failed: %d", ret);
}
return ret;
}
static int spi_ambiq_release(const struct device *dev, const struct spi_config *config)
{
struct spi_ambiq_data *data = dev->data;
if (!spi_context_configured(&data->ctx, config)) {
return -EINVAL;
}
spi_context_unlock_unconditionally(&data->ctx);
return 0;
}
static const struct spi_driver_api spi_ambiq_driver_api = {
.transceive = spi_ambiq_transceive,
.release = spi_ambiq_release,
};
static int spi_ambiq_init(const struct device *dev)
{
struct spi_ambiq_data *data = dev->data;
const struct spi_ambiq_config *cfg = dev->config;
int ret = 0;
if (AM_HAL_STATUS_SUCCESS !=
am_hal_ios_initialize((cfg->base - IOSLAVE_BASE) / cfg->size, &data->ios_handler)) {
LOG_ERR("Fail to initialize SPID\n");
return -ENXIO;
}
ret = cfg->pwr_func();
ret |= pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("Fail to config SPID pins\n");
goto end;
}
memset(ambiq_spid_dummy_buffer[0], AMBIQ_SPID_DUMMY_BYTE, AMBIQ_SPID_DUMMY_LENGTH);
am_hal_ios_interrupt_clear(data->ios_handler, AM_HAL_IOS_INT_ALL);
am_hal_ios_interrupt_enable(data->ios_handler, AMBIQ_SPID_INT_ERR | AM_HAL_IOS_INT_IOINTW |
AMBIQ_SPID_XCMP_INT);
cfg->irq_config_func();
end:
if (ret < 0) {
am_hal_ios_uninitialize(data->ios_handler);
} else {
spi_context_unlock_unconditionally(&data->ctx);
}
return ret;
}
#ifdef CONFIG_PM_DEVICE
static int spi_ambiq_pm_action(const struct device *dev, enum pm_device_action action)
{
struct spi_ambiq_data *data = dev->data;
uint32_t ret;
am_hal_sysctrl_power_state_e status;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
status = AM_HAL_SYSCTRL_WAKE;
break;
case PM_DEVICE_ACTION_SUSPEND:
status = AM_HAL_SYSCTRL_DEEPSLEEP;
break;
default:
return -ENOTSUP;
}
ret = am_hal_ios_power_ctrl(data->ios_handler, status, true);
if (ret != AM_HAL_STATUS_SUCCESS) {
LOG_ERR("am_hal_ios_power_ctrl failed: %d", ret);
return -EPERM;
} else {
return 0;
}
}
#endif /* CONFIG_PM_DEVICE */
#define AMBIQ_SPID_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static int pwr_on_ambiq_spi_##n(void) \
{ \
uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
DT_INST_PHA(n, ambiq_pwrcfg, offset); \
sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
k_busy_wait(AMBIQ_SPID_PWRCTRL_MAX_WAIT_US); \
return 0; \
} \
static void spi_irq_config_func_##n(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_ambiq_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}; \
static struct spi_ambiq_data spi_ambiq_data##n = { \
SPI_CONTEXT_INIT_LOCK(spi_ambiq_data##n, ctx), \
SPI_CONTEXT_INIT_SYNC(spi_ambiq_data##n, ctx), \
.spim_wrcmp_sem = Z_SEM_INITIALIZER(spi_ambiq_data##n.spim_wrcmp_sem, 0, 1), \
.inst_idx = n}; \
static const struct spi_ambiq_config spi_ambiq_config##n = { \
.int_gpios = GPIO_DT_SPEC_INST_GET(n, int_gpios), \
.base = DT_INST_REG_ADDR(n), \
.size = DT_INST_REG_SIZE(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.irq_config_func = spi_irq_config_func_##n, \
.pwr_func = pwr_on_ambiq_spi_##n}; \
PM_DEVICE_DT_INST_DEFINE(n, spi_ambiq_pm_action); \
DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, PM_DEVICE_DT_INST_GET(n), &spi_ambiq_data##n, \
&spi_ambiq_config##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_ambiq_driver_api);
DT_INST_FOREACH_STATUS_OKAY(AMBIQ_SPID_INIT)

11
dts/arm/ambiq/ambiq_apollo3_blue.dtsi
View File

@ -189,6 +189,17 @@
zephyr,pm-device-runtime-auto;
};
spid0: spi@50000100 {
compatible = "ambiq,spid";
reg = <0x50000100 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <4 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0>;
zephyr,pm-device-runtime-auto;
};
spi0: spi@50004000 {
reg = <0x50004000 0x1000>;
#address-cells = <1>;

11
dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
View File

@ -207,6 +207,17 @@
zephyr,pm-device-runtime-auto;
};
spid0: spi@50000100 {
compatible = "ambiq,spid";
reg = <0x50000100 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <4 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x8 0>;
zephyr,pm-device-runtime-auto;
};
spi0: spi@50004000 {
reg = <0x50004000 0x1000>;
#address-cells = <1>;

15
dts/bindings/spi/ambiq,spid.yaml Normal file
View File

@ -0,0 +1,15 @@
# Copyright (c) 2024 Ambiq <www.ambiq.com>
# SPDX-License-Identifier: Apache-2.0
description: Ambiq SPI Device
compatible: "ambiq,spid"
include: [spi-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
properties:
int-gpios:
type: phandle-array
required: true
description: |
GPIO that interrupts the SPI controller to require operation

9
modules/hal_ambiq/Kconfig
View File

@ -40,10 +40,15 @@ config AMBIQ_HAL_USE_I2C
help
Use the I2C driver from Ambiq HAL
config AMBIQ_HAL_USE_SPI
config AMBIQ_HAL_USE_SPIC
bool
help
Use the SPI driver from Ambiq HAL
Use the SPI Controller driver from Ambiq HAL
config AMBIQ_HAL_USE_SPID
bool
help
Use the SPI Device driver from Ambiq HAL
config AMBIQ_HAL_USE_MSPI
bool