Adds support for the Adafruit ItsyBitsy nRF52840 Express.
This board ships with the UF2 bootloader, so the device has
been set up so that Zephyr applications are flashed the
same way that other (Adafruit) firmware is flashed with the
UF2 bootloader.
This has been tested locally, and the button, blinky and
led_apa102 samples run without problems.
Signed-off-by: Embla Flatlandsmo <embla.flatlandsmo@gmail.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The nucleo_wb55rg platform has Bluetooth feature that
requires the HSI48.
The board DTS enables the HSI48MHz clock for that purpose.
And also selects it as the source (default) of the CLK48.
Note that the clk48 node must be enabled for any another source.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add support for loading M4 image from OCRAM when running with dual core
operation. The M7 core will copy the M4 image from flash into OCRAM, and
the M4 core will execute it there.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Flexspi partition definition is shared between both cm4 and cm7 core.
Refactor it to be in shared dtsi file. This will ensure that both cores
share the same partition information, for dual core operation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable the openamp sample for RT1170EVK. CM4 core has a custom DTS
overlay to use LPUART2 for console information, and use a secondary GPT
timer for the system tick.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for loading M4 image from OCRAM when running with dual core
operation. The M7 core will copy the M4 image from flash into OCRAM, and
the M4 core will execute it there.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Flexspi partition definition is shared between both cm4 and cm7 core.
Refactor it to be in shared dtsi file. This will ensure that both cores
share the same partition information, for dual core operation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1170 and RT1160 CM7 and CM4 cores have the same set of differences.
Merge the DTS files for both CM4 and CM7 cores, to create generic
rt11xx_cm4 and rt11xx_cm7 files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- Similar to what was done for other parts of the driver, remove any
register specification from Devicetree (modesel-reg/mask)
- Keep all the information in the driver, and define modes as "numbers",
e.g. PCA9420_MODE0: 0, PCA9420_MODE1: 1, etc.
- Bindings provide IC defaults now (all modes allowed 0/1/2/3 and
initial mode set to 0).
- When mode is controlled via the MODESEL0/1 pins (ie directly by an iMX
MCU using the dedicated PMIC_MODE0/1 pins), the driver will not allow
to select a mode (it is not possible). This mode is now enabled by
setting `nxp,enable-modesel-pins` in Devicetree. When enabled, all the
allowed modes are configured to be selectable via pins. When disabled,
mode can be set via I2C (using TOP_CNTL3 MODE0/1_I2C fields)
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Setup the appropriate voltage in the PMIC based on the
core frequency.
Add labels to the regulators for easy access to the nodes.
Add CONFIG_REGULATOR to the defconfig so we can setup the
PMIC voltages during platform startup.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The OSPI flash driver expects size in bits.
Use bits instead of bytes for the size.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Lauterbach provides the particular version of the TRACE32 limited to
use with the Arduino Nano 33 BLE. The license of it ties to Arduino Nano
33 BLE hardware serial number. It also works with the ZephyrRTOS.
Add configuration for GDB-Frontend version of TRACE32.
Limitation: This patch support only 'debug' command
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Remove regulator-fixed-sync specialization, create a single driver that
is always synchronous. The asynchronous part is rarely/never used, so
let's keep things simple for now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable RTU System Timer Module (STM) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to
133.333333 MHz.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Add a hidden Kconfig option to select the index of the target RTU
(Real-Time Unit) subsystem. This index can be used by peripheral
drivers, for example, to know the peripheral instance index since the
HAL is index-based.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
pca9420_i2c.h has neem remamed to pca9420.h (device only has I2C, so
it's kind of redundant to have i2c in the header name).
pmic_i2c.h was again not generic but designed specifically for PCA9420.
All its macros have been renamed, s/PMIC/PCA9420, and moved to the
pca9420.h header.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The driver had a conceptual issue regarding current limitation. PCA9420
is able to limit the current flowing through VIN, ie input current. This
is a global setting, not individual to each regulator. This patch
creates a new DT property: nxp,vin-ilim-microamp to specify such limit.
It is applied when the device is initialized.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Voltage ranges were hardcoded in Devicetree, however, things can be
significantly simplified by using the recently introduce linear ranges
API. All values are now computed using information stored in the driver,
so there is no need to store any lookup table in ROM. Code should now
both be faster in average and consume less ROM.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Maximum current was not specified. Even though not used, yet, it is a
valuable information. Values taken from PCA9420 datasheet, Figure 1
"Simplified block diagram".
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Regulator registers were set for each BUCK/LDO in DT, likely because of
the way the devices were instantiated. When using a generic iterator,
ie, DT_INST_FOREACH_CHILD, there's no way to differentiate the child
being _parsed_. Since instantiation happens now based on child node
names, we are able to know which registers each devices gets assigned at
the driver level. This greatly simplifies Devicetree, and it actually
removes information that is not strictly hardware description from it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Right now the PCA9420 driver instantiates by iterating over all
children. This is somewhat problematic, for a few reasons:
- Since instantiation is generic code, we're forced to put internal
details on Devicetree, e.g. reg-masks. After this change, this will no
longer be necessary.
- We take all children, regardless of what is defined in DT.
While we have no means to validate Devicetree node names as in Linux
dtschema, this approach allows us to have per-child specific
initialization code. This is somewhat similar to the Linux approach.
Note: nodelabels have been removed, since they were not used.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Activates the NOR octoflash MX25r6435f present on the disco kit
b_l4s5i_iot02a from STMicroelectronics.
The connection is made through the OSPIM peripheral for the
octospi1 pins.
QUAD spi mode is selected but SPI or DUAL are also supported.
SPI Max freq is given by the datasheet
and is compatible with Voltage Range 2.
DMAMUX is used for ospi transfer on request 40.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The random MPU faults experienced before were actually caused by a too
small system work queue stack for LoRaWAN in a custom application.
PR #52550 adds a compile-time check to avoid such issues in the future.
Signed-off-by: Martin Jäger <martin@libre.solar>
Moving the SDFP table property from the sample to the device tree
of the stm32l562e_dk disco kit.
The MX52lm51245 Nor octoflash mounted on this boarddoes not
provide its own internal SFDP parameters.
With this patch, the SFDP table is given by the board DTS.
So that the stm32 ospi driver can initialized the NOR octoflash
correctly with the parameter from that property instead of
relying on the nor octoflash.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit configures the testcase to run on the
stm32u585 target boards. USART3 is selected
Pins Tx and Rx (PD8 PD9 on CN14) must be connected on the HW board
to pass the test.
The USART transfer uses the GP DMA transfer with request
28 and 29 on 2 DMA channels (0-15).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove the CONFIG_FPU for the stm32f3_disco and
stm32373c eval boards.
The FPU exists like on many other stm32 series
but CONFIG_FPU has not to be defined here.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
No sfdp-table property given by the DTS but received from
the octoflash Node rely on the issued by the read sfdp command.
Note that the size of the mx25lm51245 flash controller
is expressed in bits (ie 512Mbits or 64 Mbytes).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
nRF52840DK documentation was updated with details on how to change UART1
pins. nRF52833DK and nRF21540 boards has the same incorrect instructions
and were not fixed. Do it now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove FLASH_SIZE setting, as this is now set from the SOC level via the
flash chosen node. Also, correct the flash controller node to the flash
device that implements flash support
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove FLASH_SIZE setting, as this is now set from the SOC level via the
flash chosen node. Also, correct the flash controller node to the flash
device that implements flash support
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add LSI clock and RTC clock source for Nucleo F103RB, L4A6ZG and
F103 mini to resolve a regression concerning the RTC counter
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Adjust the flash size of the nucleo_wb55rg board from
STMicroelectronics to the exact flash as defined by the DTS
of the stm32wb55Xg.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Added a selecion on rt6xx that allows the loading of
the safe flash clock initialization to be inside SRAM
if the user code is being executed from flash.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Embla Flatlandsmo