In some cases we cannot know the BDF up-front, so provide a way to
look it up based on the vendor and device ID.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
These have been redefined in various places - better to have them in a
single place that different users can use.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Now that we generate a header that extern's all possible devicetree
based device struct we can remove DEVICE_DT_DECLARE and
DEVICE_DT_INST_DECLARE as they aren't needed anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Renamed to make its semantics clearer; this function maps
*physical* memory addresses and is not equivalent to
posix mmap(), which might confuse people.
mem_map test case remains the same name as other memory
mapping scenarios will be added in the fullness of time.
Parameter names to z_phys_map adjusted slightly to be more
consistent with names used in other memory mapping functions.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's disabled by default. When enabled, and if the device exposes both
MSI and MSI-X capabilities: MSI-X will be selected and MSI disabled on
the device.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This enables software MSI "multi-vector" feature, letting the user to
register an isr handler per-MSI message.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Though it was noted that pcie_get_cap() is only used by MSI code so far,
there is no need to put it in msi code. If unused, linker will nuke it.
So let's move things to where it belongs to.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Originally, sys_read8 to the mapped address was added part of
the unmap API to protect OMAP mapping, i.e. in case of PCIe writes,
OMAP should not be overwritten before writes are completed.
Now that we have added dummy PCIe read in the common APIs, namely
pcie_ep_xfer_data_memcpy and pcie_ep_xfer_data_dma, for the purpose
of flushing PCIe writes; the purpose of protecting OMAP *also*
gets satisfied, randering PCIe read in the unmap useless,
so remove the same.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Introduce common API to achieve data transfer using system DMA.
"System DMA" uses the outbound memory mapped Host address,
it cannot understand Host/PCIe address.
This API will take of mapping the Host address, completing
the data transfer to/from Host memory and unmapping the window;
thus providing abstraction to the user.
Since v1:
- refactored code for the cases where we have valid mapped_addr
to improve error management logic
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Once host memory is mapped to outbound memory, PL330 can be used to
transfer data between outbound memory and local memory.
Add API for the same, we get pl330 device as well as channels to be
used for tx/rx from DT and use DMA public APIs for data transfer.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
An address might be made for 64bit though it's lower 32 bits are made of
0. Also Simplifying the overall by removing a useless variable.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
currently pcie_get_mbar only returns the physical address.
This changes the function to return the size of the mbar and
the flags (IO Bar vs MEM BAR).
Signed-off-by: Maximilian Bachmann <m.bachmann@acontis.com>
There are x86 platforms where the IRQ configuration register for PCIe
is not pre-populated and the OS needs to assign a number dynamically
by writing to the register.
In order to allocate interrupts we have to know which ones have been
hard-coded in device tree. We accomplish this by collecting these
values through the IRQ_CONNECT() macro and placing them in a dedicated
linker section (in ROM).
The full set of allocated interrupts are managed through a bitmap, and
the pre-allocated values (from the linker section) are inserted into
this upon initial runtime access.
This patch introduces a new pcie_alloc_irq() API that drivers can use
to allocate interrupt line numbers. The two in-tree drivers that were
using this API (I2C and UART) are converted to use the new API.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
We should clear the pvm interrupts (snoop and pcie pmon lite interrupt)
at source before handling them.
This will make sure that we do not lose any interrupts that may have
been asserted to interrupt controller during the handling routine.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add support for interrupt driven MSI-X PVM feature for Viper.
Function mask bit update is tracked with snoop interrupt
and vector mask bit update is tracked with pcie pmon lite
address range access detection interrupt.
Both the interrupts are required to enable this feature.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
drivers: pcie_ep: iproc: move msi/msix functions to a separate
file. This increases readability and modularity.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
File names such as pcie_ep_bcm_iproc.c / pcie_ep_bcm_iproc_regs.h
seem unnecessarily long, same with CONFIG symbols' names.
Let's shorten them by replacing 'bcm_iproc' with simply 'iproc'.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.
A coccinelle rule is used for this:
@r_const_dev_1
disable optional_qualifier
@
@@
-struct device *
+const struct device *
@r_const_dev_2
disable optional_qualifier
@
@@
-struct device * const
+const struct device *
Fixes#27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
With this refactoring of pcie directory, RC drivers are placed under
host/ directory, EP drivers are placed under endpoint/ directory and
they are completely independent of each other.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
The PCI API was originally limited to 32 bit addresses. Even though
it had code to skip over the high word in 64 bit BAR entries, it
refused to use it and returned a 32 bit value. Some devices in the
wild have default mappings from the firmware for devices above 4G.
Also remove the "iobar" API. It's dead code, we don't call it and we
don't test it. IO space BAR entries are a legacy feature from way,
way back in PCI history (I genuinely have never heard of a real device
that uses them!). And there's no difference in format between one of
these and a 32 bit "memory" BAR anyway, someone who actually had this
requirement could just use the existing API without worry.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
PCIe shell was enabled by default if shell is enabled in below commit:
commit ee985d81aa ("shell: enable modules by default if shell is
enabled").
However, this shell file has tests for PCIe RC, not applicable to EP.
So, should not be default enabled for PCIe EP.
If we add EP shell tests in future, they should be added under
drivers/pcie/endpoint/ directory.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
pcie has an all in one command for listing pci devices. Make it support
additional commands and move lspcie to `pcie ls`.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
If shell is enabled then enable all sub-shells if their dependencies are
satisfied. This was done for some modules and subsystems but was not
consistent.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support to register callback function for each PCIe reset.
These callback functions are executed from corresponding
PCIe reset interrupt handler if registered.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add reset interrupt handlers for all three types of reset
interrupts that iProc PCIe EP can receive - namely PERST,
INB PERST and FLR.
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
iProc PCIe EP IP is present in Broadcom PCIe offload chips.
Add iProc PCIe EP driver to provide basic PCIe EP functionality.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Introduce common API to achieve data transfer using memcpy
to/from outbound region of PCIe EP.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Add public APIs for PCIe endpoint driver:
- EP configuration space read/write
- Mapping/Unmapping of Host buffer and PCIe outbound region
- Raise interrupt to Host
These are minimal base APIs to make PCIe EP functional.
Also, add a Kconfig and an empty CMakeLists.txt for drivers to extend.
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.
Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.
Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Bool symbols implicitly default to 'n'.
A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.
Also replace some
config
prompt "foo"
bool/int
with the more common shorthand
config
bool/int "foo"
See the 'Style recommendations and shorthands' section in
https://docs.zephyrproject.org/latest/guides/kconfig/index.html.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Use this short header style in all Kconfig files:
# <description>
# <copyright>
# <license>
...
Also change all <description>s from
# Kconfig[.extension] - Foo-related options
to just
# Foo-related options
It's clear enough that it's about Kconfig.
The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)
git ls-files '*Kconfig*' | \
xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This trivial patch extends the PCIe shell to check for and report
on a device's ability to use MSI-X interrupt signaling.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Per guidelines, all statements should have braces around them. We do not
have a CI check for this, so a few went in unnoticed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some firmwares (looking at you, slimbootloader) don't set the registers
in PCI configuration space to indicate the IRQ routing, so we remove
the check that verifies that the user and firmware agree on IRQ number.
Also eliminate the return value of pcie_irq_enable() since no one uses
it and we can't return a meaningful value any longer.
Signed-off-by: Charles Youse <charles.youse@intel.com>
Firmware is supposed to set a register in PCI configuration space which
indicates the hardware IRQ that the endpoint is attached to.
A function is implemented which reads this register, and the PCIe shell
is updated to use it instead of doing it "manually".
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A new function pcie_irq_enable() is added to be used in lieu of
irq_enable() when the target device is PCI(e)-attached. The function
attempts to use MSI, when configured in the kernel and supported by
the endpoint; failing that, it will verify that IRQ requested is in
fact routed to the device by the boot firmware before enabling it.
The NS16550 UART driver is updated to use pcie_irq_enable().
The PCI(e) shell is extended to dump information about wired IRQs.
The up_squared devicetree is fixed (reverted?) to IRQ5 for UART1.
The galileo enables MSI by default.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Kumar Gala