Enabling pwm on timer3 for stm32l1 series in dtsi.
Adding other timer nodes for pwm capability.
Signed-off-by: Sidhdharth Yadav <sidhdharth.yadav@hcl.com>
Add support for u-blox EVK-ANNA-B1 which uses the nRF52832.
This board is similar to the nRF52dk_nrf52832 with
different pin assignments on the header pins and not having
the debug-in and shield SWD headers.
Tested with blinky, button, and Bluetooth peripheral_hr
Addressed review comments, including SW2
Rebased to pick up new board in test_adc.c - corrected typo
Reverted to sda-pin, scl-pin
Signed-off-by: Bob Recny <bob.recny@u-blox.com>
Enable the user led and user switch that can be found
on h3ulcb, they are both connected to the GPIO 6 bank.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Renesas RCar Gen3 series have up to 8 GPIOs
bank.
Add bank 5 and bank 6, that is used to manage user led and
switches on different demo board.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Add GPIO controller driver that can be found on Renesas
RCar gen3 soc series.
Controller can handle up to 32 GPIOs per banks.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The Compare match timer can be found on Renesas
RCar Gen3 soc series.
It depends on clock controller to supply clock to the
CMT module.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Compare Match Timer is a 32 bit compare match timer
that can be found on various Renesas R-Car SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Clock Pulse Generator, Module Standby Software Reset, are registers
presents in Renesas Gen3 SoC series.
MSSR is used to supply clock to the different modules, shuch as timer,
or UART, it's also possible to issue a reset the different module.
CPG registers allow to get the rate or to set some divider like for
the CAN clock.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Adding ulcb boards documentation based on Renesas official documentation
and following zephyr guideline.
The documentation is describing the board and the current
Zephyr support.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add basic configuration for H3ULCB, just enough to see the
Zephyr boot banner on the ram console.
This configuration make use of the Cortex-R7 present on
r8a977951 SoC.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Most of the Renesas RCar Gen3 based SoC contains a Cortex R7
processor.
This processor has access to the same memory mapped devices than
the Cortex-A5x cores.
- CPU operates upto 800MHz
- Can use ram area from 0x40040000 to 0x42000000
- Has 512 interrupts on GIC-400 compliant with Arm GICv2
Add support for r8a77951 as first SoC of this series which is also
known as H3 ES2.0 and is present present on different boards such as
Salvator and R-Car Starter Kit(H3ulcb).
This first SoC definition is just enough to print Hello World in a
ram console.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
The log_backend_swo_init function sets the CYCCNTENA bit of the DWT
register to 0, disabling the counter (which is necessary for the timing
functions.
Avoid overwriting the CYCCNTENA bit.
Do not try to set read-only bits.
Fixes#34341
Signed-off-by: Andrés Manelli <am@toroid.io>
Move ctx structure from struct data to struct config, so that
it can be filled at compile time and we could get rid of the bus
init routines.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Fixes a typo where the BT_GAP_PER_ADV macros had MAX twice,
as well as adding a MIN timeout macro and check.
Signed-off-by: Emil Gydesen <emil.gydesen@nordicsemi.no>
With some additional macro-magic we can remove the CMake-based header
file template feature, and instead take advantage of the usual
DT_INST_FOREACH_STATUS_OKAY() macro.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
There are no boards that need hard-coded interrupts so just remove this
build-time conditional branch. The way going forward is that all PCIe
devices should always use PCIE_IRQ_DETECT.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add new kconfigs
Include the ns-app built by TF-M build system for regression tests
Update tfm_ipc sample to use new kconfig
Signed-off-by: Andreas Vibeto <andreas.vibeto@nordicsemi.no>
Some users reported issues on Windows regarding navigation bar title
location. Scroll values have been adjusted to fix the problem. Tested on
both Linux and Windows (Chromium/Firefox).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Fix ECC thread stack size which is to small to account for the worst
case scenario. When an interrupt happens at the point where the ECC
thread is at the highest stack size usage pushing the thread context
to service the ISR causes a stack overflow.
Increase the ECC thread stack size by atleast the size of the basic
stack frame of 32 bytes aligned on 8 byte for ARM architectures.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
not all distributions install python3.8 libraries as a part of the
python3 package. Specifying the python3.8 library solves this problem.
Signed-off-by: Zach Hudson <zhudson@phytec.com>
By default ztest thread is running at the priority `-1`. This value is
invalid when the testcase is running in cooperative mode only. Set
default ztest thread priority to `-2` if this is the case. The fix is
modeled on the approach used to define the default
`MAIN_THREAD_PRIORITY`.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Sidhdharth Yadav