41960ab366
dts: bindings: can: remove optional sample point properties
...
Remove all optional, initial CAN sample point properties and rely on the
CAN timing calculations to automatically pick the preferred sample point
location based on the initial bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-03-17 15:36:19 +01:00
722e04da3c
flash: stm32: configurable write block sizes
...
Add new devicetree bindings for F4 and L1 series for configuration of
block size used in flash write operations.
Allow byte-size write operations in `flash_stm32f1x.c`. This file is
being shared between F0, F1, F3, L0 and L1 series. L0 and L1 series
allows for single byte writes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
2024-03-11 18:57:43 +00:00
23750ffd90
dts: arm: stm32h7 MPU attribute for the external Memory
...
Define the MPU attribute to be ATTR_MPU_EXTMEM for the
external region (qspi- or octo-spi NOR flash)
starting at 0x90000000 of the stm32h7 serie.
A XiP region should be Included inside with attribute
ATTR_MPU_IO, to access the external memory in XIP.
The stm32h7a/h7b serie as another external area at 0x70000000.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-03-11 14:41:08 +01:00
0418179b12
dts: stm32h723.dtsi: fix timers23 address format
...
Fixes: simple-bus unit address format error,
expected "4000e000".
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2024-03-11 14:23:25 +01:00
f1bfbb0627
dts: arm: st: wba: do not enable standby pm mode
...
Do not enable Standby low-power mode by default since the associated
Kconfig PM_S2RAM is disabled by default. Otherwise we could enter an
unsupported low-power state.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-03-04 22:14:11 +01:00
8dc3f85622
hwmv2: Introduce Hardware model version 2 and convert devices
...
This is a squash of the ``collab-hwm`` branch which converts all
in-tree boards to hardware model version 2 including build system
changes, board updates and soc conversions.
This squash is a combination of the following commits:
ca214745a1 soc: Remove soc_legacy folder and move ARM Kconfig
f12cb0979f1807bcf4d43ec2299c628ea02f4e63f2eb7652ceab509a5ee006ad037f993f9e706859204372d264f82c961a466987b2e30584484e6707ae443d1e3ce3629c64e6fc835d893d29ef2f23ebfd49b1749e1e59b7a3fd69bb0eb2581c4458890f651a4370ad196cfda66d6ec6b1d75ab774cdd59f7aa36e6640fe25709a9cf88f211b4eb21a455dfbfdc76c48a714ecafc67ddbc366c3c78e02c08f96b1b85e249558cc4013b366ce5c0b09bb472432542e816a8a3a9aeab17139a4fe97b9de615fcab94a7752f69b7f3eba827956914362bbd5a62278fd23b6a11ccec4c1067c16d2b8340b01099d81e417bec296672720fada12aa9dfe37ebac1ed32828fe6a5afba7855bca48c17723db1fd4d229a78b2552ebcc96061d96ed854e05d14fa1ae81105543040a182335ae79b3f910b7ad4f32104db555e23a41200d3c670e4e53fc7c6a060b22c2edb89c0a96dcb778be1ee1c4465e6c62137f037a3b52a47277cae6fada3e49d34ebc8424dd3b041cb52939576b43a95ce8f3e6494d550399e92708708c909e06dac41e68dd8f842b40b4d1c04978067c69089e097205b40ad8cfa6fb29c29ed228c688cfd3d6acad30c940ee9e5a10ec805650c8326882cf44be451a9c405a6ff2b536d2535ee6058710b76687602f32ae4918d0cc1dabca65a37ddce659a1393a07f6813ed00f6771317d67988cb0c51ec62b9db15c690101216ce14b4c3ca65dcdc3ef499fcabdd4ad054b5bd7ae8aa992785ceb3c1cdc20fe291c7cde2b95db8975260a47b948799f9f221c24e7869ca38abf2fb5eca3e25730ba569e3466606a09a398dcc8cb8ffc74f82291ff4b55484b7f1996cc5c2fb0c759cb580513aa9e0de7afa1480cf1cf0d719e004beb5c3e6f79a34a3640b7cf50e950e7737cfb548f505494c97a4eaf69f37aa1335caeaea9f7f30bf680db4c81b3433d7e99764ea79d19e7fd4ae6f6a836080549bd169bf8ae1d25f04d522211c2af0de8d5128f401644fbc68cadf7fe431b449094fea63bb632acc1fc1a3316ebdc71c0344f8cf0176fc25f36b920ed0f22520368d9296acfb2bc55063380b71f93394b55e7a4fd2ec101942f1d11477c8b84dd64e3e816c43a7aa2fa4984e1c17ad9a90f53ad57af9aa6529950f0bf05a3a10b614aa45abe735e939ab8f64ca9483ff8dd4df113dd534239b31287d91511e356a2c91e25ab471c231fd939417cff1e6028d4e41b1b2b520f83cbbf7899c64533f7b618668f20ea6e937cf4ff43a1c68e1fea4e3b49014a0f14f344eeab40f3f8f22d10bf79ea518727d5ca80c81ef015635836c1b699338f6f2bf19639a1b5dc981807444e5d07e824852fd081ac8666d425f5715bd38f47a900c6ef25be0c639b8378c2ef907d1d553de2ebc9b8ec0080c2eb7025e50f10ef3d4bd2ba9fdaa1d686c8d4a0ca575ac5cafb87b290730414b30055ab0012bfc15df526225ead19e7df29df0bd7d963d6795a90f9bf43d5540be7065148d8561dc9a8aa17763571e878dae301b8a319e60eef36a0a7c30f28df9a4223feed401abafffc78e5eaa44e586958fff4c31a2b865b2ffc652b5db061a4c66547845e9d95a1f96399e563eb0a628914bc58b67e8de1e781bfcc2ed18f330fc38f9fb9e06f4c384b90b30b9d0f6842e2fab2af1e1737686a4b78b8396b6bb856765299c6277efd46eb41505cbc5c42951a140701a795d28810f9a957e6f6df994e7ee88dfabd56ca447b951593bad5dfa71fad2e863f393f08e714b26734597a762908af0bccd1ceb29fca4768ccaf70ebdb0879adae82580d08c5f0defbae1e46cabce6f2f85133f286642f4e78c61e807896ca46c8abc9fbfed5f48f8cd8b1cc476f6cc57a04c4c14a54ca06c2054e5cff0e0fce1b334264c46a8b947a0e91990417bbdee12719154a437a430fbef93387f9681cf2498b1347abe812561e33786dc47f081914dbbc97349dbda9902ff58e126e1a4e72899f0257c3790c10b1eefaee62088dc34d186a571be3a9e9d360e6b400f9c4fbac27e8b4dd29a9c4380f5fdb2b9de981be056394e8a34804dbf17e19c9731f1bce53d41869d146c4f01427d285e19cf22bebd7298caf243274c2105a2bae84dca54e000afc314e8e3f9a7c2ce6d51ac56d0501c054381a7a4d93b8d9fdab2fcb1245ead4b57a7bd4c143d30670a66ac03a8a85c077998c253a99fcab883b80197c8b7a153b8dc2b911f6402366117af0a8d127452271f17a86841c2a9d993b314531abd4ea2bf70b5256e9fcc318e5cf1d51eab8628f981532f2fee1430ca6a475a9b9b41b91db0271ecbb957e2b20615a90a44454a20c113fbd34e3852a5420ad604de62e2a7b7656f7dcc2eb5eb58e90a2e9aae6e9e4541d3baac2d63b1d21483f6046e6ded90a7bf9fd79dce697c823666a35340989f0a6034b004bd43c48a6d756923d3801216b8db7cc30aaea866427ea292689b3f0eee7ebc727c8903265b2bb529a78ed5197cf636ae06d0c53f3a144e0aa066885238fc205dffc08af56545093abe4ecfa192f1bfd1e8cdc308bf067e6254833275ccdb9a70e5ea218c70cc4bfca52baf9ded1b3bcce64f362a8ae2c51dee5da92e66c35e0d0d1491a4810fa0fca79c4acd18bfaf7546c94b9588aab718c3e30f17424a435a97cb524fdc20fdff622dc2b63912f1e33a2e6c47c37d3db7a788b9a187046b92d41253ee9638cccb4c633242d4acf9230a60d28969a0409e51d3f1b2528df1baf1096e7ca0b1db9c53de9874671e2ba6c01407133ad4a51ca9812f3d54ec76b1fbeca649789e4336b3bdb736493dda5ee4be48e1f5d5bf11cf73df1ac73ed6dcd0fdbe3552e854cff3905a87ea5bc0a706e5d27cdd1edcdd0880f7add89cab6edad8d68c58e0822a6b987093a802096fd4652830f9c5a82527cd9d8cd83af7d0c1cfd9b84d4573c72fe863c37dfacbf9e1108d7b0edbed44a5c2840448c5a9f31273692c035b5d33ef03b84b9910ada00d0e7b9fb2103f89e1f9a533fbc3f92f65b287646b74aaffea54ddcd9d47f1878b1ae42be236b83bd1a9ecc39c26f09ed29d03c970b74acec315cfee6d8676e008b5d939224e357d6232c5f9dcce04da061646f15956a69b880324f77079893e0d11146f92b227bed5d1bb4cd325f95ec20d055676307c7a415d92cd15144f582a63ff71bcbb53c6f412c83eb4fc069715685b19f5b9ef9410612b297707acdcea932bc0a3ae2b22320b4ce17d547c65400d659ec56f9e6dc5977dbbaa6e492854399f248e04815f16834e6c1ee449ef1db4deddf9d2fd3ed43d2902fceb173d716ca1a10b7abc8942869b334f54b614611a5285821b9ec2e04cbad174e24ca0febfc9a32559a2dc4b11e025197edd05be39cf624c410b40bf25e5e71600d7e952bd84a1bc59dc342143b10392d693db2def8ed3abf7d3efe78c579770e1d91315401092efcefc089d9b295a85ba2f56bdcd500314155dfb08819dff756456c16e591f9198dc496f1bafbf9b290f25baa9fbe6bf19144bcfe57c74c86af7eaeb4f852f738bac9789264a954e1722d7e8515b24125246c21ef09396eb2e670c004fd83e3daa98e79a2de60c6dae877ce9cec2b50218c234a65f55916cc6e6be01fa83730326888e5959f1795e06e8663d517d3cc2468f9aeddabccf4f48f014a6e286a3b12e375f826b4db917de9d6e0d27efebc16a7a72728348838439c68231ba9986e9619fde82932e787cb9339f88f1cd4c3465492eadf06b8a8659e170b359133d7256d466429eda1ff441eb3ef82a8255c282204758a8ca93411958a947f446d324cb41153963c74df1c8d518ce5040fef0cef5be52ccc244fc7426eca5e1eba9d8a8f8d92edc72775117d1b2d0b0384b56ac1b77b223d91a077b2ab413b6c2a404f572ba24fcb348c7edf811ad90566d44ef90cf8c860f205defba98a17635c156a2d35cfc47a3a4b37129b4e44a923beba5dd242b2703b9c80d4e64428268c493833ad2b5bc640daa94f2d2b0dbb9d51ee6f7697ac594e4bad6ba5803ba099db8c27545630177cf53d486504cf24dd0672a64cc1565b3d146dd2723314ee1ce24a421952d559f29e12c3d8bd0ffbc1da33be52dfb7b64c29d1827f5b4a9556fd69e5d87a155e4ace1bbe2762460a64fdc3913e769c9c3a09a1109edc296f7bfcdbbe8f0fbb543983073e0f8080197a19f3961616fc8ae55622077738a6289516e4439d83688316e65f09c4862efd5a21dede0f6cd391e864ea2947ec3e416b52f797a227433db339f9a646d3f2d5d0d434bf86c3f5ed8157eecff8ee7a34507614f6f02b56cb96600c55c92af294bfc5e4882524d2a04bce0e9b39d0229c771f23a0570e64b6d3e1764f499f3e79029ae6b1804dfe2c90da5c3d4d46698cb1afbf01589f9897c872f7fb2030c7718643266232c4bdc0c47b64c638a8156ee8ad8a3d33dadeb04fee7371d2ad37a0c222cf85b7169f44b67ac4307dbb65d3715e79cb957d12bd83a2181a135ec3524dbe97e5ead632b90043cc1a30f24bdf0df9000bd2c7972a9a202c2bf447c3e36f2042b9dd58aea10e1898b093286f4a7524d1709cdb378f040cff2c8c90fae8e0c828dcc60ec79f1b0d943584b30fc194024d940e8053c3a8dfd5473b76fef5792b05e7ff202daa8ee66cbc294533b47b2edbbaeebd31d273b257a3f985de0888ec867960a8916ca677ed3abcf4ad19d40ac386683f9242c3c78f248d17f1600a67265e99f8d44317ee400343d17ed783ef549a643aeac552e601d643442f7a387b32519752efcd06263dd71766b0df5526fa07bd94198f6f0726dd7b155a7031804697afa5d2f001e320ec7f7b3c3089dfcddc7eeb724eb6a76f1043cde6cab924cbfb237fdff91803042b7704767b94414e07fa3a3d79ba01d3beca7ce84f4041b988bae5766fbf39c7264a418784421e79ba15f6ffdcb60185d6acb08d3e90e592ffd1eb8a7e3441ada469f2370342433187c10248d96421ddc5e6a65500f3ef21e7baf09ede5bae4a64803b0bd70c8cd52eab9e836f2835cb11ca36d331d2662cc4e09bdd9bc29769353da23ffbacc932b424cea9b140fd52e025943a1c7347686a9debd98799adab07c42f642aacdcdf48637066d3e983bc2a2361e0f32716a1688ff64135fb22859910e5d1122bc319cb19f011725ccac1400f7f6a4f8d8486139085b9eee7e8dafbd638e43ecd12f4155db2390e9d9ba8195cdc8e94b85361c970127fc2394c75373cf2a1cc871428f3f25945c3e480f740fd5847123f76ba9a0587719baa88505060a61ae199584be1c52dc8933942a5b004663b77c2c333e5c14ff98650bcdc268ccf0c8ba92e1fb54fe330772ba3639b2adbc5ed79f5ce6d493aa3a28086a9ca1b2a511d06ce281f09abcdb5364fd7768f173dcb21bbbbd9cbbab426569358f8fe82ba37e9084070d467e7053a5f2808d7ccbbb73e7550e9094afc4da1712cdd535be404b365baaa697ab269ecab3c902a572e3fb0ecfbf42757e0191d03bb4454648976f0ad6ee6b81f5e228ec8834bdb615e8f27fa8de2f8633a903807e0bd2c0724d7f625dc157a8cde534ec99c31b0a21546140a43f01ab6de60c16bcb8b2db228d73073fc26225c6b62d90114fa845af3095c8c3c3be03c02db12907eeb723cb74f9461d068a821de8532ba580c7236eb272ddf1958ed121c3ab0d70959d3b1088baadc18d867b0a9ee6ede7119b48e70ead914d2b955da9c4ac6a20214b57f56d7f3b173be1805b50f6691a188e01a1222c53e97b553f3b181b09f19a2075ab8928b1628cda3a7486870d704bd204789e1068e384307e3dced025df674994b6e173173b30a04cf83b133c207847a12f1e467f4c8d2a15326b5bfc0cfd5e691b4ac9c235741f198c3a761e438e6cad495e34da7c1313717df76392c3969ed8f245d764d8f71bb7b4fe27d23aad080823b860e72e4483decbed94669e3c01af5a7b81e563b4ca376e484adae34412f7fe29be50e2ca9bbbed12c2f4f5ec7ff8fd8d1b9f20030bd34b31ec20d0dcbb602ed6af4631b175003a4de231b911daa9597f6d99644828c8186ab2bd430d88d3ddcc40ccc0204e1dd9972d782a2c2e1406d2d9c62e118e8ba99dc599a939166049c4d94844dfeaf4ffba187f08271214526be24a5cd921d2b97b3c04051fca73a9e75338d87bcc16719335857856f9fe5429d9dc78e402535113e8923b276aee9a4795f8d611b2d82646443959786f12d81670db2e98980430aadac020f66e05140e4551a77d640e0c90131e1c15936b63787a7ae02fc5047f38f7bb223d3cca3580e6a8a0c1647faf22185cee94762ecdc9afcc27e053e4a17018f9188fdcd78fcaa41cb5ddbc413f7f76be3d4bc80f4442fa698ec5fbd67f7d3ef220460a223f284b5c381edcb7397401c7d2ae7a3243a24bec82c690d94f6f9b636209235ab6ee5b18859074c750818f98d3896caa442cff42c42c2df4ca9cb3970f90f713a70ee9ccd3cda715faedc56a543f387147f88c465f5dc5b8c7db2b6efd885dddac5a26ae5c4e7fdef834a12d03ab7830625a0c2ca049127ff3654b76e02f43c0a1bfcf1d9746e621ee43f219b14976891c52b0d39f0e0a973f66f592b64c94bcb4b2ac8fdc7ed6eb0770376250da6d8b92e86a5f8e5daa15ee799cc5f8aa8ce4ac84e203c14c7312265ee04c12ae3bcbcc5321c1dbebcc06c60aedb9e46010ca988adee7d7dc2c9db0cc506675b7c3abb7920734f52bc646ea712b5005bbaa55141a11f026f70ebbd854a3af8c9edefa8fd61bbfb5ba2a4d1980c35
2024-03-02 16:56:33 -05:00
109a045e57
dts: stm32h723.dtsi: Add missing timer definitions
...
Added missing timers23/timers24 definitions.
Signed-off-by: Samuel Kleiser <s.kleiser@vega.com>
2024-02-27 14:14:27 +00:00
23d3114db3
dts: boards: stm32h562: Add missing UART7 and UART8
...
UART7 and UART8 instances were missing in the device tree for
STM32H562.
Signed-off-by: Linus Isberg Martinsson <isberg.linus@gmail.com>
2024-02-02 09:29:18 -06:00
7ba1f2e6d8
dts: arm: stm32wba: add standby mode to device tree
...
Add standby mode to device tree
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2024-01-30 18:01:00 +01:00
b772e366c9
dts: stm32u5: Add SW/JTAG debug port node
...
Provide jtag port pins description, so they can be used to be set in
analog mode when not required to save power (around 40uA saved in total).
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2024-01-26 15:52:38 +00:00
c1ae6e5b4e
soc: stm32g0: add fdcan2
...
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
2024-01-25 16:01:40 +00:00
c9263db28f
drivers: can: bosch: mcan: use int0 and int1 as interrupt names
...
Consistently use "int0" and "int1" as interrupt names for CAN controllers
based on the Bosch M_CAN IP core. This aligns with the upstream Linux
bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-01-09 18:28:30 +01:00
ed6da68f5b
i2s: stm32h7: add i2s support for stm32h7 mcu family
...
This commit modifies the I2S driver to work for STM32H7
family of MCU's. Currently only TX is working.
Tested on nucleo_stm32h743zi. Requires dma1 & dmamux1 to be enabled.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
2024-01-04 13:48:28 +01:00
800edb2b69
dts: arm: stm32f7 declares sram0 as zephyr, memory-region
...
Declare the SRAM0 region as memory-region
for the stm32f745 serie. Will be included for the stm32f746
for the stm32f765 serie. Will be included for the stm32f767
for the stm32f722 serie. Will be included for the stm32f723
Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-12-22 09:53:39 +01:00
79e55c2a04
dts: wba: configure HSI16 as RNG clk source
...
We might have to do this differently:
Configure rng default clock in .dtsi
Set board specific config in .dts
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2023-12-18 17:31:08 +00:00
2c88daab3b
dts: stm32wba: Define SRAM6 as RAM_NOCACHE
...
SRAM6 is used by RF and should be defined as RAM_NOCACHE
to allow unaligned access reads.
"IO" might be a better match but is not available on this arch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2023-12-18 17:31:08 +00:00
a54a52b085
dts: arm: Add support for STM32F722 SoC
...
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.
Signed-off-by: Evan Perry Grove <evan@4grove.com>
2023-12-13 13:57:55 +01:00
7c3853537e
dts: boards: stm32h562: Adding USART11
...
This commit is enabling the USART11 for STM32H562/563 boards.
Signed-off-by: Alexis LECOQ <alexis.lecoq@hidglobal.com>
2023-12-13 09:41:57 +01:00
4ba3aedfed
dts: arm: st: add SMBus devices
...
Add SMBus devices to all SoCs which have either
a st,stm32-i2c-v1 or st,stm32-i2c-v2.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2023-12-12 10:57:41 +01:00
3bbc2cc9e1
dts: stm32wba: Introduce stm32wba55Xg package
...
Based on stm32wba55, stm32wba55Xg is similar from device tree description
to stm32wba52Xg.
Take the opportunity to fix stm32wba52Xg descriuption scheme which was
missing stm32wba52.dtsi.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-12-05 14:53:39 +00:00
a65ebbd6bc
dts: arm: stm32f7 vref calibration address fixed
...
This PR set the correct value for the stm32F7 devices.
And change vrefint-cal-addr to <0x1FF07A2A> for stm32F722-F723
soc serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-12-04 14:46:54 +01:00
5b3d4598a7
dts: arm: Blanket remove all usages of arm,num-mpu-regions
...
This removes all occurrences of arm,num-mpu-regions relying on the value
reported by the register instead.
A user may still define this property if they need to have a compile time
definition for it.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-01 10:48:00 +00:00
82d7535b19
dts: st: Add cpu node labels
...
After porting from h5 to f7 i noticed that not all mcus have
cpu node labels. Added cpu0 node labels to all stm32 dts.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
2023-11-27 12:21:19 +00:00
c3940cb4f7
Revert "dts: arm: stm32u5 family has a x2 factor on its LPTIM clock"
...
This reverts commit 823b0e6016
2023-11-27 12:18:41 +00:00
86cf5829a4
dts: arm: stm32: add stm32f303xb bindings
...
The STM32F303xB is very similar to the xC, the only difference being the
RAM and flash sizes.
Signed-off-by: Martin Gritzan <martin.gritzan@gmail.com>
2023-11-24 09:24:14 +01:00
3387c57a94
dts: stm32f4: set RTC as idle timer by default
...
Only RTC can be used as the idle timer for cortex-m systick. Set the
chosen node as RTC by default.
The idle timer will be enabled only if PM management is set.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-22 09:28:53 +00:00
c6bba39f4d
dts: stm32wl: Configure LPUART wakeup line
...
Rather than configuring in serial_wakeup sample, define LPUART1 wakeup
line in wl.dtsi file.
Additionally make few cosmetic changes to nucleo_wl55rj overlay in
serial wakeup sample.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-11-21 14:22:22 +01:00
43ef398614
pm: add power management for stm32f4x
...
Add soc power management for the STM32F4x chips.
One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.
The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.
The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
2023-11-21 08:46:17 +00:00
aeb1e8ed34
dts: arm: st: add STM32U5A9 support
...
add STM32U5A9XJ device trees. Also add ADC2 & ADC1_2 dual mode nodes
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
2023-11-21 08:44:34 +00:00
176d433b98
drivers: bbram: stm32-bbram: port to stm32wl
...
On STM32WL, the backup memory is defined as part of the TAMP peripheral.
This seems to be a deviation from the stm32 family where this memory is
defined as part of the RTC.
The STM32WL reference manual shows that tamp_pclk is connected to
rtc_pclk. This means that the clock required to run the TAMP peripheral
is the same as the RTC's. A quick port of BBRAM on STM32WL is achieved
by instanciating the bbram device as a child of the RTC and by modifying
the address offset to the first backup register from the rtc base
address.
Signed-off-by: Adrien Bruant <adrien.bruant@aalberts-hfc.com>
2023-11-21 08:40:51 +00:00
d15f5bbcc7
dts: arm: st: h7: add support for stm32h7b0
...
Add device tree support for STM32H7B0 line.
Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
2023-11-15 10:02:06 +01:00
56395ec42f
dts: arm: st: Update stm32l496.dtsi
...
Add missing master-can-reg into stm32l496.dtsi
Signed-off-by: William MARTIN <william.martin@muxen.fr>
2023-11-09 11:22:48 +01:00
9bb44b8e5f
dts: arm: st: set flash size for stm32l011X4
...
This device lost the reg property since 88c9d1fbaf
2023-11-09 09:09:22 +01:00
9e74efd159
dts: stm32wba: Add rtc node
...
Add RTC node for stm32wba series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-11-08 15:11:27 +00:00
5067e543fa
dts: st: Add all missing l010 SoCs
...
Add minimal devicetree entries to enable the whole stm32l010
SoC family.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2023-11-06 10:14:10 +01:00
88c9d1fbaf
dts: st: Move eeprom from stm32l010 to stm32l010Xb
...
The variants of this family have different sizes of eeprom. This moves
eeprom definition from common family definition to device specific.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
2023-11-06 10:14:10 +01:00
8242ef0a37
soc: arm: st_stm32: stm32l0: Add support for STM32L081
...
Add support for the STM32L081xx soc series.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
2023-11-06 10:11:40 +01:00
72aee4b90b
drivers: clock_control: stm32: add an option to enable CRS for HSI48
...
for nucleo_stm32g0b1 board.
the HSI48 clock is the clock used by default for the USB controller,
however its default tolerance is not enough for the USB specification,
leading to some random errors depending on many factors, including the
upstream HUB or host.
this commit adds an option in the device tree to enable the STM32 Clock
recovery system (CRS) using USB SOF packet reception as a reference,
which brings the HSI48 within the required accuracy for USB transfers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
2023-10-26 09:47:48 +02:00
52d47fcf96
dts: stm32wba: Add GPDMA support
...
Add GPDMA1 node description to STM32WBA devices.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-10-20 15:05:59 +02:00
6424949dfd
dts: arm: stm32: add AES1 peripheral to stm32wb family
...
STM32WB MCUs has two AES peripeherals. Add AES1 definition, AES2 must not
be used by application CPU core.
Signed-off-by: Lukasz Hawrylko <lukasz@hawrylko.pl>
2023-10-20 15:05:26 +02:00
f8e812aa3f
dts: arm: st: u5: correct lptim2 clock enable bit
...
The LPTIM2 clock enable is bit 5 of RCC APB1 clock enable register 2
(RM0456 Rev 4 11.8.34).
Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
2023-10-09 10:17:07 +02:00
c2175e9ed5
dts: arm: st: u5: add stm32u5a5 dtsi
...
Add STM32U5A5 dtsi.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-09-29 10:34:33 +02:00
950fba73ee
dts: arm: st: u5: add missing compatibles for stm32u595 and u599
...
Add missing compatibles for STM32U595 and STM32U599.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-09-29 10:34:33 +02:00
58ca047fa7
dts: stm32h7: flash-controller: Add default STM32 as compatible
...
Add "st,stm32-flash-controller" as compatible for STM32H7 so that
what is defined for STM32 in general is also defined for STM32H7.
Already most of the other STM32 versions have this addition.
Also removed the specific STM32H7 flag check in
/flash/driver/Kconfig.stm32.
Signed-off-by: Stefan Petersen <spe@ciellt.se>
2023-09-29 09:47:46 +02:00
1c67228428
dts: stm32: stm32u5: Add sdmmc1 and sdmmc2 configuration
...
Provide the soc configuration for sdmmc1 and sdmmc2 controllers.
This includes registers address, clocks, resets and interrupt line
details.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
2023-09-29 09:46:08 +02:00
9783ed56d9
dts: bindings: can: deprecate the sjw and sjw-data properties
...
Update the descriptions for the various CAN devicetree timing properties
specified in Time Quanta (TQ) to make it clear that these, if present, are
only used for the initial timing parameters.
Deprecate the (Re-)Synchronization Jump Width (SJW) devicetree properties
for both arbitration and data phase timing as these are now only used in
combination with the other TQ-based CAN timing properties, which are all
deprecated.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-09-28 16:28:56 +02:00
6d6d7b5607
dts: arm: st: add st,adc-sequencer properties to all stm32 adc
...
Add st,adc-sequencer to all STM32 ADC instances.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-09-22 15:30:47 +02:00
fa1f33316d
dts: arm: st: remove sensor channels from stm32 adc nodes
...
Remove temp-, vref- and vbat-channel from STM32 ADC nodes as it is not
used in the driver anymore.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-09-22 09:21:34 +02:00
2baac8e769
soc: Add support for STM32F072X8
...
Adds support for the STM32F072X8 SOC, which is a variant of the
existing STM32F072XB with less flash.
Signed-off-by: Jonas Otto <jonas@jonasotto.com>
2023-09-19 15:25:09 +01:00
e4a125b6a4
dt: Make zephyr,memory-attr a capabilities bitmask
...
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-09-15 12:46:54 +02:00
Henrik Brix Andersen