soc: st: Migrate stm32h7 series to new hw model

Migrate STM2H7 series to new HW model.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>

drivers/clock_control/clock_stm32_ll_h7.c

@@ -90,8 +90,8 @@
 
 /* Datasheet maximum frequency definitions */
 #if defined(CONFIG_SOC_STM32H743XX) ||\
-	defined(CONFIG_SOC_STM32H745XX) ||\
-	defined(CONFIG_SOC_STM32H747XX) ||\
+	defined(CONFIG_SOC_STM32H745XX_M7) || defined(CONFIG_SOC_STM32H745XX_M4) ||\
+	defined(CONFIG_SOC_STM32H747XX_M7) || defined(CONFIG_SOC_STM32H747XX_M4) ||\
 	defined(CONFIG_SOC_STM32H750XX) ||\
 	defined(CONFIG_SOC_STM32H753XX)
 /* All h7 SoC with maximum 480MHz SYSCLK */

soc/soc_legacy/arm/st_stm32/stm32h7/Kconfig.series

@@ -1,18 +0,0 @@
-# ST Microelectronics STM32H7 MCU series
-
-# Copyright (c) 2019 Linaro Limited
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_STM32H7X
-	bool "STM32H7x Series MCU"
-	select ARM
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_FPU
-	select SOC_FAMILY_STM32
-	select HAS_STM32CUBE
-	select CPU_HAS_ARM_MPU
-	select HAS_SWO
-	select USE_STM32_HAL_CORTEX
-	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
-	help
-	  Enable support for STM32H7 MCU series

soc/soc_legacy/arm/st_stm32/stm32h7/Kconfig.soc

@@ -1,132 +0,0 @@
-# ST Microelectronics STM32H7 MCU line
-
-# Copyright (c) 2019 Linaro Limited
-# Copyright (c) 2020 Teslabs Engineering S.L.
-# Copyright (c) 2021 Electrolance Solutions
-# SPDX-License-Identifier: Apache-2.0
-
-config STM32H7_DUAL_CORE
-	bool "Dual Core"
-	depends on SOC_SERIES_STM32H7X
-
-choice
-	prompt "STM32H7x MCU Selection"
-	depends on SOC_SERIES_STM32H7X
-
-config SOC_STM32H723XX
-	bool "STM32H723XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H725XX
-	bool "STM32H725XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H730XX
-	bool "STM32H730XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H730XXQ
-	bool "STM32H730XXQ"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H735XX
-	bool "STM32H735XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H743XX
-	bool "STM32H743XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H745XX
-	bool "STM32H745XX"
-	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
-	select CPU_HAS_ICACHE if CPU_CORTEX_M7
-	select CPU_HAS_DCACHE if CPU_CORTEX_M7
-	select STM32H7_DUAL_CORE
-
-config SOC_STM32H747XX
-	bool "STM32H747XX"
-	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
-	select CPU_HAS_ICACHE if CPU_CORTEX_M7
-	select CPU_HAS_DCACHE if CPU_CORTEX_M7
-	select STM32H7_DUAL_CORE
-
-config SOC_STM32H750XX
-	bool "STM32H750XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H753XX
-	bool "STM32H753XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H7A3XX
-	bool "STM32H7A3XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H7A3XXQ
-	bool "STM32H7A3XXQ"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H7B0XX
-	bool "STM32H7B0XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H7B0XXQ
-	bool "STM32H7B0XXQ"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H7B3XX
-	bool "STM32H7B3XX"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-config SOC_STM32H7B3XXQ
-	bool "STM32H7B3XXQ"
-	select CPU_CORTEX_M7
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-
-endchoice
-
-config STM32H7_BOOT_M4_AT_INIT
-	bool "Boot M4 core during M7 init independent of option byte BCM4."
-	default y

soc/st/stm32/Kconfig

@@ -39,4 +39,38 @@ config STM32_ENABLE_DEBUG_SLEEP_STOP
 	  effectivly destroys the use-case of `west attach`. Also
 	  SEGGER RTT and similar technologies need this.
 
+choice POWER_SUPPLY_CHOICE
+	prompt "STM32 power supply configuration"
+	default POWER_SUPPLY_LDO
+	depends on SOC_SERIES_STM32H7X
+
+config POWER_SUPPLY_LDO
+	bool "LDO supply"
+
+config POWER_SUPPLY_DIRECT_SMPS
+	bool "Direct SMPS supply"
+
+config POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO
+	bool "SMPS 1.8V supplies LDO (no external supply)"
+
+config POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO
+	bool "SMPS 2.5V supplies LDO (no external supply)"
+
+config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+	bool "External SMPS 1.8V supply, supplies LDO"
+
+config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+	bool "External SMPS 2.5V supply, supplies LDO"
+
+config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT
+	bool "External SMPS 1.8V supply and bypass"
+
+config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT
+	bool "External SMPS 2.5V supply and bypass"
+
+config POWER_SUPPLY_EXTERNAL_SOURCE
+	bool "Bypass"
+
+endchoice
+
 endif # SOC_FAMILY_STM32

soc/st/stm32/soc.yml

@@ -90,6 +90,26 @@ family:
     - name: stm32g484xx
     - name: stm32g491xx
     - name: stm32g4a1xx
+  - name: stm32h7x
+    socs:
+    - name: stm32h7a3xx
+    - name: stm32h7b0xx
+    - name: stm32h7b3xx
+    - name: stm32h723xx
+    - name: stm32h725xx
+    - name: stm32h730xx
+    - name: stm32h735xx
+    - name: stm32h743xx
+    - name: stm32h745xx
+      cpuclusters:
+      - name: m7
+      - name: m4
+    - name: stm32h747xx
+      cpuclusters:
+      - name: m7
+      - name: m4
+    - name: stm32h750xx
+    - name: stm32h753xx
   - name: stm32l1x
     socs:
     - name: stm32l010x4

soc/st/stm32/stm32h7/CMakeLists.txt

@@ -8,4 +8,6 @@ zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c)
 zephyr_sources(mpu_regions.c)
 zephyr_linker_sources(SECTIONS sections.ld)
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/st/stm32/stm32h7/Kconfig

@@ -0,0 +1,82 @@
+# ST Microelectronics STM32H7 MCU series
+
+# Copyright (c) 2019 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32H7X
+	select ARM
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select HAS_STM32CUBE
+	select CPU_HAS_ARM_MPU
+	select HAS_SWO
+	select USE_STM32_HAL_CORTEX
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+	select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
+	select CPU_HAS_ICACHE if CPU_CORTEX_M7
+	select CPU_HAS_DCACHE if CPU_CORTEX_M7
+
+config SOC_STM32H723XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H725XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H730XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H730XXQ
+	select CPU_CORTEX_M7
+
+config SOC_STM32H735XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H743XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H745XX_M7
+	select CPU_CORTEX_M7
+
+config SOC_STM32H745XX_M4
+	select CPU_CORTEX_M4
+
+config SOC_STM32H747XX_M7
+	select CPU_CORTEX_M7
+
+config SOC_STM32H747XX_M4
+	select CPU_CORTEX_M4
+
+config SOC_STM32H750XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H753XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H7A3XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H7A3XXQ
+	select CPU_CORTEX_M7
+
+config SOC_STM32H7B0XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H7B0XXQ
+	select CPU_CORTEX_M7
+
+config SOC_STM32H7B3XX
+	select CPU_CORTEX_M7
+
+config SOC_STM32H7B3XXQ
+	select CPU_CORTEX_M7
+
+if SOC_SERIES_STM32H7X
+
+config STM32H7_DUAL_CORE
+	bool "Dual Core"
+
+config STM32H7_BOOT_M4_AT_INIT
+	bool "Boot M4 core during M7 init independent of option byte BCM4."
+	default y
+
+endif # SOC_SERIES_STM32H7X

soc/st/stm32/stm32h7/Kconfig.defconfig

@@ -8,10 +8,7 @@
 
 if SOC_SERIES_STM32H7X
 
-source "soc/soc_legacy/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7*"
-
-config SOC_SERIES
-	default "stm32h7"
+rsource "Kconfig.defconfig.stm32h7*"
 
 config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h723xx

@@ -5,9 +5,6 @@
 
 if SOC_STM32H723XX
 
-config SOC
-	default "stm32h723xx"
-
 config NUM_IRQS
 	default 163
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h725xx

@@ -5,9 +5,6 @@
 
 if SOC_STM32H725XX
 
-config SOC
-	default "stm32h725xx"
-
 config NUM_IRQS
 	default 163
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h730xx

@@ -6,10 +6,6 @@
 
 if SOC_STM32H730XX || SOC_STM32H730XXQ
 
-config SOC
-	default "stm32h730xxQ" if SOC_STM32H730XXQ
-	default "stm32h730xx" if SOC_STM32H730XX
-
 config NUM_IRQS
 	default 163
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h735xx

@@ -5,9 +5,6 @@
 
 if SOC_STM32H735XX
 
-config SOC
-	default "stm32h735xx"
-
 config NUM_IRQS
 	default 163
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h743xx

@@ -5,9 +5,6 @@
 
 if SOC_STM32H743XX
 
-config SOC
-	default "stm32h743xx"
-
 config NUM_IRQS
 	default 150
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h745xx

@@ -3,12 +3,12 @@
 # Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_STM32H745XX
+if SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4
 
-config SOC
-	default "stm32h745xx"
+config STM32H7_DUAL_CORE
+	default y
 
 config NUM_IRQS
 	default 150
 
-endif # SOC_STM32H745XX
+endif # SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h747xx

@@ -3,12 +3,12 @@
 # Copyright (c) 2019 Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_STM32H747XX
+if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4
 
-config SOC
-	default "stm32h747xx"
+config STM32H7_DUAL_CORE
+	default y
 
 config NUM_IRQS
 	default 150
 
-endif # SOC_STM32H747XX
+endif # SOC_STM32H747XX_M7 || SOC_STM32H747XX_M7

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h750xx

@@ -5,9 +5,6 @@
 
 if SOC_STM32H750XX
 
-config SOC
-	default "stm32h750xx"
-
 config NUM_IRQS
 	default 150
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h753xx

@@ -5,9 +5,6 @@
 
 if SOC_STM32H753XX
 
-config SOC
-	default "stm32h753xx"
-
 config NUM_IRQS
 	default 150
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h7a3xx

@@ -5,10 +5,6 @@
 
 if SOC_STM32H7A3XX || SOC_STM32H7A3XXQ
 
-config SOC
-	default "stm32h7a3xxQ" if SOC_STM32H7A3XXQ
-	default "stm32h7a3xx" if SOC_STM32H7A3XX
-
 config NUM_IRQS
 	default 155
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h7b0xx

@@ -5,10 +5,6 @@
 
 if SOC_STM32H7B0XX || SOC_STM32H7B0XXQ
 
-config SOC
-	default "stm32h7b0xxQ" if SOC_STM32H7B0XXQ
-	default "stm32h7b0xx" if SOC_STM32H7B0XX
-
 config NUM_IRQS
 	default 155
 

soc/st/stm32/stm32h7/Kconfig.defconfig.stm32h7b3xx

@@ -5,10 +5,6 @@
 
 if SOC_STM32H7B3XX || SOC_STM32H7B3XXQ
 
-config SOC
-	default "stm32h7b3xxQ" if SOC_STM32H7B3XXQ
-	default "stm32h7b3xx" if SOC_STM32H7B3XX
-
 config NUM_IRQS
 	default 155
 

soc/st/stm32/stm32h7/Kconfig.soc

@@ -0,0 +1,103 @@
+# ST Microelectronics STM32H7 MCU line
+
+# Copyright (c) 2019 Linaro Limited
+# Copyright (c) 2020 Teslabs Engineering S.L.
+# Copyright (c) 2021 Electrolance Solutions
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32H7X
+	bool
+	select SOC_FAMILY_STM32
+
+config SOC_SERIES
+	default "stm32h7" if SOC_SERIES_STM32H7X
+
+config SOC_STM32H723XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H725XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H730XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H730XXQ
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H735XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H743XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H745XX_M7
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H745XX_M4
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H747XX_M7
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H747XX_M4
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H750XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H753XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H7A3XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H7A3XXQ
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H7B0XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H7B0XXQ
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H7B3XX
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC_STM32H7B3XXQ
+	bool
+	select SOC_SERIES_STM32H7X
+
+config SOC
+	default "stm32h7a3xx" if SOC_STM32H7A3XX
+	default "stm32h7a3xxq" if SOC_STM32H7A3XXQ
+	default "stm32h7b0xx" if SOC_STM32H7B0XX
+	default "stm32h7b0xxq" if SOC_STM32H7B0XXQ
+	default "stm32h7b3xx" if SOC_STM32H7B3XX
+	default "stm32h7b3xxq"if SOC_STM32H7B3XXQ
+	default "stm32h723xx" if SOC_STM32H723XX
+	default "stm32h725xx" if SOC_STM32H725XX
+	default "stm32h730xx" if SOC_STM32H730XX
+	default "stm32h730xxq" if SOC_STM32H730XXQ
+	default "stm32h735xx" if SOC_STM32H735XX
+	default "stm32h743xx" if SOC_STM32H743XX
+	default "stm32h745xx" if SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4
+	default "stm32h747xx" if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4
+	default "stm32h750xx" if SOC_STM32H750XX
+	default "stm32h753xx" if SOC_STM32H753XX