Move setting soc_num_cpus into its own SYS_INIT function such
that we can ensure it happens as one of the first things. We
need soc_num_cpus set before soc_mp_init is called but also before
interrupt controller init functions might be called.
Also, by having it in its own function, it ensures that
soc_num_cpus gets set regardless of how CONFIG_MP_MAX_NUM_CPUS
is set. Since if CONFIG_MP_MAX_NUM_CPUS=1, we do not call
soc_mp_init().
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
\MTL SOF is not compiling when
8d0eb6ce10
(devicetree: remove deprecated DT_CHOSEN_*_LABEL macros)
is applied
Fix - zephyr/toolchain used to be included by
devicetree/zephyr.h. The file has been removed by 8d0eb6ce10
Include is needed for ALWAYS_INLINE macro
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
When CONFIG_MP_MAX_NUM_CPUS=1, which it does for some tests, we will
get compiler warnings with soc_adsp_halt_cpu(), so only build it
when CONFIG_MP_MAX_NUM_CPUS > 1.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
We look at the Intra DSP communications capability register (DFIDCCP)
to determine the number of cores. There might be a better way to
determine the number of cores, but this works for now.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Basically:
- Name RAMABLE_REGION as "RAM";
- Insert the relocation hooks for gen_relocate_app.py.
Also, to help with "rimage" peculiarities, `fix_elf_addrs.py` changed to
not copy empty sections to output, as this would prevent someone trying
to move all of some section (such as BSS) to a different location and
reuse the platform linker script - which would generate an empty section
anyway.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.
As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.
Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Xtensa is the odd one out by using _data_start/_data_end instead. Using
the Zephyr standard helps avoid ifdefs for common code, like tests.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Fix a bug where an IPC message is sent while the peer/host ack for
the previous message has not yet been processed. There is existing
logic to check 'idr' INTEL_ADSP_IPC_BUSY bit, but this leaves
the following race:
- DSP: msg A sent by DSP to host
- HOST: IRQ, msg A acked, host sets DONE bit -> ADSP_IPC_BUSY cleared
- DSP: msg B sent by DSP to host, IPC_BUSY is clear so proceeding to send
-> e.g. 'devdata->sem' is reset --> BUG!
- DSP: IRQ, msg A done
-> e.g. call to 'sem_give(&devdata->sem)' which is wrong as
the semaphore was just reset in previous step for msg B
Add additional state to track handling of the acks. This allows
to postpone sending message B (in above example), until message A
is fully processed.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Update Intel ADSP timer driver to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove setting 'default y' for the timer driver in
Kconfig.defconfig.series as that is now handled in the driver Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus(). This is to allow
runtime determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add #ifdef CONFIG_SMP around code that only needs to exist when
SMP is enabled.
Also include ksched.h to get decleration of z_sched_ipi.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Change for loops of the form:
for (i = 0; i < CONFIG_MP_NUM_CPUS; i++)
...
to
unsigned int num_cpus = arch_num_cpus();
for (i = 0; i < num_cpus; i++)
...
We do the call outside of the for loop so that it only happens once,
rather than on every iteration.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Fixes boot failure on CAVS platforms with
CONFIG_NO_OPTIMIZATIONS=y by moving z_soc_mp_asm_entry
into .text linker section to ensure it is copied to
SRAM.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Sometimes IPC message acknowledgement should be done by external
code to provide sufficient timing (example assemble code related
to powering down). Added bool return type to ipc message done handler
that if callback function returns true, IPC API skips writing
IPC message completion bits.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
The restore vector after power gating was configuring the MEMCTL register
incorrectly. This caused an FW crash during the cache prefetch.
Additionally, since lp sram cache issue was fixed, xtensa hal function
can be replace with zephyr equivalent.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Continue to phase out MP_NUM_CPUS, change Kconfig to be
MP_MAX_NUM_CPUS and make MP_MAX_NUM_CPUS the main Kconfig symbol.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The commit boot code does not call hp_sram_pm_banks() so there is
no need to do an extern declare.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The functions to get memory bank counts are simple enough that
they can be always inlined. This mostly helps with debugging,
especially with NO optimizations, as inlining is being done only
if the inline keyword is specified. This creates a chicken and
egg problem where the SRAM init functions need to call these
before code copying can be done. However, these functions are
not in memory before code copying, resulting in jumping into
memory with random bits.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is a "load" flag associated with segment to be copied
into Xtensa attached memory during manifest parsing. So only
copy those segment if indicated so. There may be some segments
in the struct with NULL destination address. So this is
to avoid memcpy into NULL.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is an assumption in parse_module() during code/data copying
that the memory has already been zero-ed, and hence no need to
clear memory when a BSS segment is encountered. In CAVS ram
initialization code, bbzero() is called. However, in ACE code,
there is no such call. So add them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The `ARCH` init level was added to solve a specific problem, call init
code (SYS_INIT/devices) before `z_cstart` in the `intel_adsp` platform.
The documentation claims it runs before `z_cstart`, but this is only
true if the SoC/arch takes care of calling:
```c
z_sys_init_run_level(_SYS_INIT_LEVEL_ARCH);
```
Which is only true for `intel_adsp` nowadays. So in practice, we now
have a platform specific init level. This patch proposes to do things in
a slightly different way. First, level name is renamed to `EARLY`, to
emphasize it runs in the early stage of the boot process. Then, it is
handled by the Kernel (inside `z_cstart()` before calling
`arch_kernel_init()`). This means that any platform can now use this
level. For `intel_adsp`, there should be no changes, other than
`gcov_static_init()` will be called before (I assume this will allow to
obtain coverage for code called in EARLY?).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
MTL is just one platform and this code is going to be used in multiple
platforms currently under development, so reduce the confusion and move
to a common namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
File still not being removed due to out-of-tree usage. We will drop it
once the external code has stopped referencing it.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Split the defines based on domain and cleanup ace_v1x-regs.h so we can
finally remove it and stop include soc specific headers across the tree.
Future generations of this family will be able to use the same naming
scheme without having to use the version name in the file name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Now that we have shim defined for each platform, no need to support all
platforms within the same struct. This change exposes some bugs where we
were relying on the old structure and calling into unused register space
for example for SRAM initialization on some SoC generations.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup soc.h and move interrupt defines into own headers. Rename some
of the defines for ACE to have a unified namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The DW register block was duplicated into the ACE header while we had
the same thing in the driver. Move everything to the driver as the first
step with further improvements planned on top of this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The file uses architecture specific IRQ calls without including
appropriate headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
With the incoming removal of kernel.h/types.h from init.h, lots of files
start to show compile errors because they relied on indirect
definitions, including errno.h.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Kumar Gala