Adds supporting code that allows the RAM load mode of MCUboot to
be used and for applications to build successfully with it.
Sysbuild can be used to build images for this mode
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Rework PM handling to use pm_device_driver_init(). Shim is not using
put and get internally as there is no api that disables or stops
pwm so it is hard to determine when to put the device. There are cases
when PWM peripheral is stopped but PWM is still active because
duty cycle is 100% or 0% and pin is driven by GPIO and not PWM.
If user want to use runtime PM with PWM it is possible and getting
the device will initialize internal data and putting will suspend
by forcing PWM stop if used and setting pins to sleep state. However,
from power consumption perspective it is enough to set 0% or 100%
duty cycle on all channels.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Shim was not correctly disabling PWM when it was not used. Task
STOP was triggered but PWM->ENABLE remained set which caused
increased current. Added interrupt and enabled event handler in
the nrfx driver to allow disabling PWM on STOPPED event.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Use NRFX_FOREACH_PRESENT macro to iterate over all PWM instances
and create device only for those enabled in the devicetree.
This approach removes need of changing driver code when new
instance id is added.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Supported memory attribute for device for Cortex-M.
Not sure why such code was conditional compile for only Cortex-R,
but Cortex-M also suited.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Fix the DMAMUX driver for the STM32C0 HAL update. Typedef used in function
is now const.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
STM32C0 have a different prescaler for SYSCLK and for HCLK.
Updates the clock driver to use the appropriate prescaler for each series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
What is changed?
1. Updated the data sync barrier to make sure the other parameters of
`arm_cpu_boot_params` are updated before updating its member `mpidr`
2. Updated the MPIDR affinity level mask to account for affinity level
1 and 2 along with level 0.
Why do we need this change?
1. As reported in issue #76182, on Cortex_A_R, the current code
execution fails to consider the correct sequence of data sync
barrier and cache maintenece for the code to work on non cache
coherent cores in SMP enabled mode.
The secondary cores are waiting in a loop for primary core to set
`arm_cpu_boot_params.mpidr`. As soon as primary core set this,
the secondary cores start reading other parameters from the
`arm_cpu_boot_params` however, the existing position of DSB
instruction doesn't guarantee that `arg`, `cpu_num` and other
parameters of `arm_cpu_boot_params` would be updated before `mpidr`
is udpated and this could lead to a unpredicatble behaviour so,
we need to move the DSB instruction.
2. The affinity level mask is updated because it didn't account for
level 1 to identify individual cores within a cluster and
level 2 to identify different clusters within the system which can
lead to an incorrect conversion between mpidr to core-id.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
What is the changed?
CPU affinity test for SMP cores will now cover a change in ROM offset.
How is it changed?
Add a new testcase section with ROM offset set to something other than
the default 0.
Why is it change?
There is no test to cover the issue reported in #76182 and the cpu
affinity test is the closest to test the issue. Adding a new testcase
will makes sure there is no breaking change in the future.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
What is changed?
Secondary cores can now boot successfully on cache and non-cache
coherent systems if the Zephyr image/vector table is loaded at an
address other than the default address 0x0.
How is it changed?
1. By calling the relocate_vector() from reset.S as part of EL1 reset
initialization instead of prep_c to have VBAR set for all cores and
not just for the primary core.
2. Remove dead code under CONFIG_SW_VECTOR_RELAY and
CONFIG_SW_VECTOR_RELAY_CLIENT.
Why do we need this change?
1. As reported in issue #76182, on Cortex_ar, VBAR is set only for
the primary cores while VBAR for the secondary cores are left with
default value 0.
This results in Zephyr not booting on secondary cores if the vector
table for secondary cores is loaded at an address other than 0x0.
VBAR is set in relocate_vector() so we move it to reboot.c which is
better suited to have configs related to system control block.
2. The two SW_VECTOR_RELAY configs have a direct dependency on
CONFIG_CPU_CORTEX_M, which is disabled while compiling for
Cortex-A and Cortex-R hence leading to a dead code.
How is the change verified?
Verified with fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Enables the XSPIM2 rail when using GPIO bank N
Enables the XSPIM1 rail when using GPIO bank O or P
Enables the USBvoltage detector when using the GPIO M
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change adds a release note informing about the newly introduced Kconfig
option for Bluetooth stack.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Use a separate workqueue instead of system workqueue for connection TX
notify processing. This makes Bluetooth stack more independent from the
system workqueue.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Fix build of nrf_qspi_nor flash driver without multithreading enabled.
This is required for builds like mcuboot.
Signed-off-by: Joakim Andersson <joerchan@gmail.com>
Defining OPENOCD and OPENOCD_DEFAULT_PATH when we are using sysbuild
doesn't make any effect.
This updates flash.cmake to make these variables compatible with sysbuild.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
This commit updates picolibc module so that CMAKE_BUILD_TYPE is not
defined by picolibc when building with Zephyr.
The avoids a situation where both picolibc and Zephyr defines the
optimization level, for example like: `-Os -O2`.
And remove the warning:
> CMake Warning at .../zephyr/CMakeLists.txt:2166 (message):
>
> The CMake build type was set to 'MinSizeRel', but the optimization
> flag was set to '-O2'.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Remove explicit CAN controller sample-point/sample-point-data values and
instead rely on the defaults, as they change with the configured bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Apply selection from the hash URL *after* having sorted the vendors
alphabetically.
Remove the initial call to updateBoardCount() as it is useless to
have one this early.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Fix a regression introduced at the last minute when cleaning up
the stylesheet. The rule as it was made no sense.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
It is undefined behaviour to shift / add offsets to a null pointer.
Move to direct offset tracking to satisfy UBSAN.
Simple translation of code:
buf0 -> buf
buf +=/++ -> offset +=/++
buf = -> buf+offset =
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
The stm32l4 devices were previously assigned the generic STM32 AES driver,
which turned out to be incompatible with the stm32l4 series. This commit
updates the nodes to use the new driver specifically designed for this
series.
Add missing node for stm32l4a6, stm32l4q5, stm32l4s5 and stm32l486 socs.
It appears stm32l4p5 and stm32l496 socs do not have the AES accelerator
present, so the nodes are removed from the dts files.
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
This patch resolves compiler warnings related to mismatched pointer types
between the STM32L4 and generic STM32 AES HAL by introducing CAST_VEC
macro.
Fix github CI warning
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
This patch completes the addition of support for the STM32L4 AES
accelerator by introducing conditional handling for different STM32 AES
HAL variants. Key changes include:
- Created device tree bindings `st,stm32l4-aes` for STM32L4 AES
- Replaced `copy_reverse_words` with `copy_words_adjust_endianness`
to handle endianness conversion for different variants.
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
This patch introduces a unified function pointer approach to handle
encryption and decryption operations for the STM32 AES accelerator.
- Replace separate `do_encrypt` and `do_decrypt` functions with a generic
`do_aes` function, using function pointers to AES HAL functions.
Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
Drop preprocessor redefinitions
Some preprocessor defines were redefined to follow
stm32 hal naming conventions.
People seems to be confused by redefines and use
them with alternating names.
This PR does not change code behaviour,
but shall increase it's readability.
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
Jordan Yates