This adds the SoC specific bits to enable GDB stub,
mainly the description for the register file, and
memory regions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds basic support for GDB stub on Xtensa. Note that
this only provides the common bits on the architecture side.
SoC support is also required to fully enable GDB stub on
each Xtensa SoC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the architecture interface so that the GDB stub can
deal with breakpoints and watchpoints. By default, weak
functions are implemented to indicate breakpoints and
watchpoints are not supported.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some architectures may require memory accessed to be aligned to
certain size and cannot be accessed byte-by-byte during memory
read/write in GDB stub. This adds the ability to specify
the alignment via kconfig. The existing byte-by-byte access is
retained as it is simplier code.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds bits for architectures, SoCs or boards to restrict
memory access in GDB stub. This is mainly to make sure
GDB stub only read/write to memory that can be legally accessed
without resulting in memory faults.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Storing the state where this is the first GDB break can be done
in the main GDB stub code. There is no need to store the state
in architecture layer.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds a new function gdb_bin2hex() to convert binary into
hexadecimal string representation. This is similar to
bin2hex() but does not force a null character at the end
of the output buffer. This avoids an issue where the last
character of the hexadecimal string is replaced with
null character before sending to GDB.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This corrects the directory pointing to sample in the README
file. Also changes the TCP port number for the second serial
port exposing the GDB stub. This allows QEMU itself to expose
GDB interface through port 1234, and Zephyr's GDB stub at
port 5678.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need to bail out of the debugging session if there
are recoverable errors, for example, erroneous GDB packet
received, cannot write to certain registers, etc. So simply
send an error message to GDB and continue the GDB stub main
loop for more debugging.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds architecture-specific functions to read/write registers.
This allows architecture to have a sparse representation of
the register file as not all registers are saved during context
switches. This saves some runtime space, and provides some
flexibility on what architectures can do.
Remove from header the need to define ARCH_GDB_NUM_REGISTERS as
it is no longer used in the common gdbstub code.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds some architecture-specific functions to read/write
registers for the GDB stub. This is in preparation for the actual
introduction of these functions in the core GDB stub code to
avoid breaking the build in between commits.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
If an incoming GDB packet is bigger than what the buffer can hold,
stop putting the extra characters into the buffer. This will still
read till the end to acknowledge the packet but will return error
instead. This allows the GDB session to continue instead of hanging
or timed out due to packets not being acknowledged.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a kconfig to specify the buffer size for GDB packet
I/O. Some architectures may need a bigger buffer for the general
register packet, and we don't want it to overflow our buffer.
This also changes the packet read/write buffer to be allocated
outside of stack. Since the buffer can be large enough that it
won't fit inside the stack.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
RT600 uses the mcux flexspi driver, which can produce RWW hazards when
calling code linked into flash (such as the logging subsystem). Disable
logging in flexspi driver by default for RT600 series.
Fixes#40744
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit sets the minimum RAM requirement for the full newlib test
(`cpp.libcxx.newlib`) to 24 KiB so that only the target platforms that
can provide sufficient RAM area for the newlib heap are selected.
In case of the newlib full variant, the minimum required newlib heap
size, specified by CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE, is 8192.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The RISC-V architecture linker script was including `cplusplus-ram.ld`
linker script before `__data_region_start`, and this caused the content
of `.gcc_except_table` section to be not copied to the RAM by the
`z_data_copy` function; leading to the C++ exception handling
malfunction.
This commit relocates the `cplusplus-ram.ld` linker script inclusion
such that the contents of the relevant sections are properly copied by
the `z_data_copy` function.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit adds support for IMX6SX PWM.
The PWM module is the same module present on the IMX7D and so dts
bindings has been renamed following the one present on linux.
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Arduino compatible boards should have a working UART on pin 0 & 1.
On frdm_k64f this is handled by uart3
Unfortunately pinmuxing of uart3 was destroyed when enabling NETWORKING,
because the uart3 RX/TX pins was reconfigured for 1588 timers.
1588 timers are enabled by the enet child node, ptp which by some reason
is enabled by default.
1588 timers aren't needed in most cases when ethernet is being used,
so this fix ensures ptp is by default disabled. Likewise pinmuxing of
the 1588 timer functionality is now dependant of ptp being active
Signed-off-by: Kim Bøndergaard <kim.boendergaard@escoglobal.com>
Add support for LPSPI DMA mode on RT1064, RT1060, RT1050, RT1024,
RT1020, RT1015, and RT1010 evaluation boards. Update tests to match.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds DMA support to NXP's LPSPI driver. This can be enabled by selecting
the KConfig symbol CONFIG_SPI_MCUX_LPSPI_DMA, and requires the LPSPI
instances enabled in the devicetree to have valid DMA instances
assigned.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Without this change, when DTS SPI device node has node ID = <0>, the
value of 0 is assigned during SPI configuration and written to
whichPcs member in master_config structure.
This value wrongly overrides the default value read from NXP's DSPI
HAL (kDSPI_Pcs0 = 1U << 0).
Such situation occurs on ip_k66f board, where the DSA device -
controlled via SPI has the node ID equal to 0 (i.e. reg = <0>).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Mcuboot's bootutil libraries has option to use hooks which
allows to customize its behavior while proceeding on images
date. This patch introduces configuration options required for
enabling that option.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
The commit adds CONFIG_OS_MGMT_TASKSTAT_ONLY_SUPPORTED_STATS
Kconfig option that disables code filling in task statistics, for
mcumgr command `taskstat`, that are not collected or supported by
Zephyr.
Setting this option to y will skip following statistics in response:
"runtime", "cswcnt", "last_checkin" and "next_checkin".
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit adds note on MCUMGR SMP over serial update that corrects
problem where CRC16 length was not added to a packet length.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Improve calculation of matrix and move calculations from workflow to the
testplan script. We now generate a file that can be parsed by the action
with the data needed to start twister with the right number of nodes.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not invoke --integration when dealing with one platform only and
generate testplan only for the needed platforms.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The test is wrongly assuming that all the archs have #address-cells =
<1> and #size-cells = <1> at the DT root. This is not always true, and
it makes the test failing for AArch64. Fix the wrong assumption.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This platform is slow on some tests and times out on non-hardware
related tests, so exclude it or increase timeout for some of the tests
to avoid false negatives in the test results due to timeouts.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When populating bt_df_per_adv_sync_iq_samples_report the
rssi was not wrapped in sys_le16_to_cpu.
Signed-off-by: Jakob Krantz <jakob.krantz@u-blox.com>
Add some basic custom 802154 L2 tests, verifying that a custom L2 can be
integrated with Zephyr properly.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
ll_adv_set stores poitner to direction finding TX configuration.
When ll_reset is executed the pointer was not NULL assigned.
That lead to erroneous behavior e.g. df_cfg->is_enabled was set
to TRUE even the functionality was not enabled.
DF configuration is stored in memory pool. The memory pool uses
free elements to store its internal data. On reset whole pool is
expected to be free, so ll_adv_set->df_cfg may not point to any
element allocated from memory pool.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This commit is enabling the Debug support clock
like the stm32L0 or F0, the APB peripheral clock enable register 1
has a bit to clock DBGMCU before use.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is controlling the WWDG during the Stop mode in debug.
WWDG1 is frozen while the core is in Debug mode, setting the bit
of the DBGMCU APB1 peripheral freeze register (DBGMCU_APB1FZ2)
for the stm32MP1 soc devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is controlling the WWDG during the Stop mode in debug.
WWDG1 is frozen while the core is in Debug mode, setting the bit
of the DBGMCU APB3 peripheral freeze register (DBGMCU_APB3FZ1)
for the stm32H7 soc devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Following definitive transition to dts pinmux then pinctrl api
remove C pinmux api leftover definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
These two test cases both are fault injection test cases,
and there are designed for testing some negative branches
to improve code coverage. But I find that this branch
shouldn't be tested, because the spinlock will be locked
before a procedure performs here, and then it will trigger
an assert error and the process will be rescheduled to the
handler function, and terminated the current test case,
so spinlock will never be unlocked. And it will impact
the next test case in the same test suite(the next testcase
will be never get spinlock).
Signed-off-by: NingX Zhao <ningx.zhao@intel.com>
Daniel Leung